Hello i have a custom board and it has a CYCLONE V 5CSEBA5U23I7 on it.
on our custom board the HPS and the FPGA share the reset pin. both are getting the power on reset from the same source at the same time. e.g. when i switch on the FPGA boots from its own QSPI and the HPS loads the preloader from its own QSPI. both are power on independently.
i am not sure how to make the power on sequence.
the FPGA must need to boot first from the HPS if i am using H2F master and H2F lw bridge in the FPGA?
Here is what happens. when i power on my device i see that the H2F master and H2F lw bridges are not initialized automatically by the HPS. Although they exist in my QSYS project.
Then i manually initialize both bridges manually in the baremetal application in HPS firmware.
Now if i flash my program on the HPS and do a power on. the program on the HPS traps. and i think it traps because it does not see the H2F bridges.
but if i flash the *.sof on the FPGA and then start my HPS then every thing works perfect.
is there any one who can suggest me what should be the power on sequence required if i want to use the resources of the FPGA on the HPS?
As mentioned in my question.
the FPGA and the HPS are booting from its respective QSPI.
HPS is connected to QSPI, and FPGA is connected to another QSPI.
They are booting up independently.
Here is what is found.
1) when i use a baremetal project and GOD forbid if i have some where in my HPS c baremetal code a "printf" used. then the HPS is not booting up at all.
when we checked from the debugger it was running perfectly. but as soon we make a boot image for the HPS code with "printf" in it the HPS is not booting. the HPS traps somewhere.
2) the HPS and the FPGA boots up independently. The HPS boots up faster then the FPGA in independent booting mechanism. The HPS code waits on the line of the c code where it will communicate with FPGAs pio peripheral. As soon as the FPGA boots. the peripheral is available for the HPS to and then the HPS proceeds onwards.
so what i analyzed is that it doesn't matter if the HPS starts up first or FPGA. if the HPS is using the peripherals it will wait on the same line of c code as soon as it is available it will proceed.
If you have the HPS to use the FPGA peripherals, the FPGA will need to be configured before HPS can proceed, which you are observing. Thus, you will need to enable the bridges first, then program/configure the FPGA.
You can do the FPGA programming from preloader, the steps are describe below for reference:
You may refer to our Cyclone V Device Design Guideline before for other feature/information.