agilex 5 lpddr4 connection

[Dany2]

Hi guys

I have to design a board with the agilex 5, and lpddr4.

The configuration is similar to the agilex 5 premium evaluation kit (two 16 bit channels connected to the single 32 bit). CA/CS/CLK signals need to be split between the two channels A,B

Since I can't find a layout file on the internet, I want to ask whether T-line  should be used for those signals, or something else.

Regards

Dany

[KhaiChein_Y_Intel]

Hi Dany,

Are you looking for the layout file for LPDDR4 in Agilex 5? If yes, please find the user guide here

7.3. LPDDR4 Layout Design Guidelines - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/lpddr4-layout-design-guidelines.html

7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-1-6-1-0/fpga-emif-ip-parameter-for-lpddr4.html

8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning - https://www.intel.com/content/www/us/en/docs/programmable/817467/24-3-1/fpga-emif-ip-pin-and-resource-planning-80533.html

Thanks

Best regards,

Khai

[KhaiChein_Y_Intel]

Hi Dany,

I hope my previous reply was helpful. Please do not hesitate to reach out if you have any further questions.

Thanks

Best regards,

Khai

[KhaiChein_Y_Intel]

Hi Dany,

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks.

Best regards,

Khai

[Dany2]

Hi 

Thanks for your support, I was sure that my profile was configured so I will receive an email when someone answer me, but it wasn't

Sorry, and thanks once again