altgx alignment word boundaries

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

altgx alignment word boundaries

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I'm using the altgx block with four channels running at different transfer rates (all based on a 125 MHz pll_inclk). With and without 8B10B encoding enabled. In order to align I use manual bitslipping, but on some channel I am unable to receive the correct training sequence. When I simulate the design in modelsim it seems to be releated with the transport delay introduced between TX and RX. The parallel bit width is 32 bit.

Sending the alternating sequence of x"12345678" and x"90ABCDEF" and bitslipping and checking until RX_BITSLIPBOUNDARYSELECTOUT turns 0 again, I can see the almost correct RX-DATA:

EF123456 - 7890ABCD

CDEF1234 - 567890AB

Reversing the byte order won't help. Any hints on what I'm missing?

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