altlvds_tx Stratix III

[Altera_Forum]

Hello, 

when I use the altlvds_tx megafunction, it has a default setting of "tx_coreclock" for registering the input data (which I leave as set). Does this setting require that I enable the tx_coreclock output and use this to clock the logic feeding data into the megafunction or should I use the clock which I feed into tx_inclock? I've read the megafunction user guide but it doesn't appear very clear what the user should do in this situation. Thanks

[Altera_Forum]

Hello, 

 It's always best to register the incoming data with the tx_coreclk, this is an internal connection within the logic and you don't have to turn on the tx_coreclock output port. If you want to forward the tx_coreclock to an output pin, then you would turn on this port.  -- Desert Rat

[Altera_Forum]

OK, thanks. 

 So if I'm correct, I can use tx_inclk to drive the logic preceding the lvds function which is then re-registered by tx_coreclk. I think I have since read somewhere in the Altera documentation that when tx_inclk and tx_coreclk are the same frequency, I can use either to drive data into the lvds function. i.e. it doesn't matter either way.

[Altera_Forum]

Generally that's true, the tx_inclock drives the PLL, so registering with it vs the tx_coreclock usually does not matter. However, depending on the placement of the parallel data in your device, you may need one level of synchronization from the parallal domain to the high speed domain. The tx_coreclock is the best phase match to the high speed serial clock in the SERDES logic, that's why the altlvds wizard defaults to coreclk instead of inclk.  

 If you get timing violations in the altlvds_tx function, the most likely cause is from registering with tx_inclock instead of tx_coreclock. It's just something to watch out for.  -- Desert Rat