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21618 Discussions

asi output clock

Altera_Forum
Honored Contributor II
‎01-21-2009 09:21 AM
1,345 Views

I had a problem with the asi output clock. At the output rx_data_clk I've put a pll and i've connected it to the inpiut inclk0, but when i've compiled i got this error: 

Error: Clock input port inclk[0] of PLL "pll_3:inst30|altpll:altpll_component|pll_3_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block 

Info: Input port INCLK[0] of node "pll_3:inst30|altpll:altpll_component|pll_3_altpll:auto_generated|pll1" is not connected 

 

What shpoud I do?
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Altera_Forum
Honored Contributor II
‎01-28-2009 08:43 AM
642 Views

You should probably try to rearrange your project and let the input of your PLL come from an external dedicated clock input. 

Cheers. 

OD
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