avalon bus, miss reading data

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

avalon bus, miss reading data

990 Views

Hi all,

I have a Verilog RTL design which perform polynomial reconstruction. This hardware functional unit is activated by 'start' signal and gives 'done' signal once it has finish it computation.

The hardware functional unit is running at 50MHz, and from the simulation waveform, it takes around 17.16us (see attachment) to finish computation, which is about 50M*17.16u, 858 cycle count. However, when I integrate the hardware functional unit into embedded system and download onto Stratix II, the computation time I get is roughly 8M (see Attachment). This make no sense.

Anyone has any idea what is the reason that cause different clock count?

Thanks and Regards,

ty6

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.