[beginner] various questions on Cyclone V E DDR3 Hard Memory Interface pinning

[Altera_Forum]

Hi, 

 I am a student and at the beginning of learning on Cyclon V DDR3 design. I have choosen the 5CEFA7F23C8 to be "my" FPGA. I've been reading the various design resources but I'm still unsure about certain points. Unfortunately I'm missing the great system overview so forgive me for the probably stuipd questions. I want to use two 4 GB (x16) DDR3 SRAM H5TQ4G63MFR-H9C (http://www.farnell.com/datasheets/1641692.pdf) , each selected by CS.  I have some questions assigning pins. Names taken from Cyclone V *.xls - file or datasheet of H5TQ4G63MFR. 

1. H5TQ4G63MFR-H9C Adressline A15 is not available (see datasheet p. 6/33). Why is this the case? (General understanding) What am I to do with this (now free B_A_15) pin at the FPGA? Can it be used as I/O even when making usage of the Hard Memory Interface? 
2. H5TQ4G63MFR-H9C Adressline A12 and A10 have alternate functions, too (BC and AP). Will these functions be usable despite I'm using the Hard Memory Interface? 
3. H5TQ4G63MFR-H9C has DQL
4. Is (FPGA) B_DQS_2, B_DM_2 and all pins ending on B_xxx_2 associated to B_DQ_
5. Regarding the unused FPGA pins B_DQ_
6. The FPGA hast B_ODT_0 and B_ODT_1 but my memory IC has only one ODT pin - which one shall I use ? both ? is it important which one I use or can this be configured in software later on ? 
7. Same goes to B_CKE_0 and B_CKE_1 

  Sorry for such much writing and questions ... maybe somebody can help. I'm getting mad slowly but surely - but that should be pretty normal :)  Thanks in advance, Greetings from Germany   Michael