bidirectional inout of my signal

[Altera_Forum]

Hello all, 

 I have this signal calls Sync that I need to be able write the signal when I want to drive the signal. I also need to read this signal too.  So, I have 4 phases discriminator to phase them all out to 90 degree angle for solar panel charger up to 200V output to battery bank.  The fpga need to read the Sync signal from charger and to generate phase discriminator, but sometime the charger didn't give the Sync during that period time, so I need to generate my own signal for that. I need to be able read/write the Sync signal for backup plan by not to depend on charger hardware. I look at couple of sample so me how to use inout  module test(  input clk, // The standard clock  input direction, // Direction of io, 1 = set output, 0 = read input  input data_in, // Data to send out when direction is 1  output data_out, // Result of input pin when direction is 0  inout io_port // The i/o port to send data through  );    reg a, b;     assign io_port = direction ? a : 1'bz;  assign data_out = b;    always @(posedge clk) begin  b <= io_port;  a <= data_in; endendmodule   How do I use this in testbench?  Thanks, Sean

[Altera_Forum]

What do you mean with  

--- Quote Start ---   How do I use this in testbench?   --- Quote End ---   Bidirectional ports can be simulated, and you can read from/write to them at the testbenchlevel.

[Altera_Forum]

--- Quote Start ---  Hello all,  I have this signal calls Sync that I need to be able write the signal when I want to drive the signal. I also need to read this signal too.  So, I have 4 phases discriminator to phase them all out to 90 degree angle for solar panel charger up to 200V output to battery bank.  The fpga need to read the Sync signal from charger and to generate phase discriminator, but sometime the charger didn't give the Sync during that period time, so I need to generate my own signal for that. I need to be able read/write the Sync signal for backup plan by not to depend on charger hardware. I look at couple of sample so me how to use inout  module test(  input clk, // The standard clock  input direction, // Direction of io, 1 = set output, 0 = read input  input data_in, // Data to send out when direction is 1  output data_out, // Result of input pin when direction is 0  inout io_port // The i/o port to send data through  );    reg a, b;     assign io_port = direction ? a : 1'bz;  assign data_out = b;    always @(posedge clk) begin  b <= io_port;  a <= data_in; endendmodule   How do I use this in testbench?  Thanks, Sean  --- Quote End ---   Hello were you able to find the right code? Well I am working on bidireactional inout of the signal so can you help me out?