bitstream to netlist

[Altera_Forum]

Hi everyone: 

 Is there a way to check that my netlist is equivalent to the bitstream that is generated?

[Altera_Forum]

Yes. Put it in the part and see if it works. (I'm joking). 

By netlist, do you mean the RTL? If so, the answer is no. There is no way to turn this into something understandable. (Altera probably understands it, but for equivalency you generally want a third party tool. Having Altera check its own synthesis algorithms is generally counter-productive, as it's far too easy to make the same mistake twice). There are Formal Verification tools. They would check the post-fit netlist(basically the timing simulation model) against the original RTL. There was a big push for these as ASIC designers started using FPGAs, as it makes complete sense with an ASIC, since you can't try the device in system before tape-out, and it's so expensive to fix a mistake(both in $ and time). But when asked why they needed to do it for FPGA design, they generally just said, "Because that's what we do for ASICs". From what I've heard, formal verification is not easy, and I would generally recommend against it unless it was an absolute requirement or there was a really good reason. I was joking a bit, but being able to run the FPGA in-system tends to be a much better test than formal verification or huge timing simulations. (I'm sure there are varying opinions on this...)

[Altera_Forum]

firstly, Thank you for your prompt response! 

 Secondly, I totally agree with your opinions on the testing, but there is almost no flexibility in my task.   I was asked to verify 2 sections of a particularly large project: RTL to Netlist -> using equivalence checking tools. (conformal, formalpro, formality)  and Netlist to Bitstream -> the part I'm stuck at.   What I found out in my readings were that the bitstream contained config data for the connection switches, and couldn't that somehow be decompiled into netlist information? I know that there was a company who did this, but ran into legal troubles with Altera. I was hoping that there'd be another way around this predicament I'm in.

[Altera_Forum]

Decompiling the bitstream into netlist information is not something an FPGA vendor will do, as most customers would frown on that tool, to say the least. In many applications the bitstream can be viewed when configuring the FPGA(i.e. a third party could snoop that data). There are all sorts of ways to encrypt/protect this, but many applications don't do that. If it would be easy convert this bitstream to an understandable netlist, it would be easy for people with nefarious intentions to do harm(steal IP, modify systems, etc.) Because of this, there are no easy tools for decompiling the configuration bitstream.

[Altera_Forum]

After getting back to my professor on this matter, we've decided that we're going to avoid this area altogether.  

 to be honest, it was getting near shakey ground. One last question if you don't mind:  What sort of tools will allow me to view the bitstream?  Thanks for your help, Rysc!

[Altera_Forum]

That's the thing, there are no tools for viewing the bitstream. (I've had numerous occasions where a user has a bitstream in the field working for years, and then realize they have to make a change, but they've lost the original design files, or don't know which is which. They want to re-create the design from the bitstream, but there is no way to do it. 

On that note, it's good practice to store the entire project that builds an image that gets released, just in case.

[Altera_Forum]

thank you again!  

 my experience with this community has been nothing but helpful!