max v tri-state i/o

[Altera_Forum]

Hi, I need to use the tristate i/o feature of max v and can't seem to find the i/o block in the megawizard library.  

 Anybody know how to use the feature ?

[Altera_Forum]

What do you mean? An output is usually tristated in behavioral code, e.g. pin <= 'Z'

[Altera_Forum]

I have a pin which is both an input and an output. In certain clock cycles the block reads the value and in others it drives it.

[Altera_Forum]

--- Quote Start ---  I have a pin which is both an input and an output. In certain clock cycles the block reads the value and in others it drives it.  --- Quote End ---  Then you would drive the signal with a tri-state that has an output-enable, i.e., in VHDL  bidir <= 'Z' when (enable = '0') else output;  and you can read bidir as an input at any time; when enable = '0' you are reading what is driven onto the pin by the external device, and when enable = '1', you will read what you are driving on 'output'. You can turn on the 'weak pull-up' or 'bus hold' on the pin for bidir so that it is always in a valid logical state.  Cheers, Dave

[Altera_Forum]

Dave, will the Fitter automatically map my enable signal to the output enable of the i/o block ? Because in the pin assignment editor i don't see an option. 

Thanks.     --- Quote Start ---  Then you would drive the signal with a tri-state that has an output-enable, i.e., in VHDL  bidir <= 'Z' when (enable = '0') else output;  and you can read bidir as an input at any time; when enable = '0' you are reading what is driven onto the pin by the external device, and when enable = '1', you will read what you are driving on 'output'. You can turn on the 'weak pull-up' or 'bus hold' on the pin for bidir so that it is always in a valid logical state.  Cheers, Dave  --- Quote End ---  

[Altera_Forum]

Why don't you just implement a simple circuit and watch the results in the Quartus netlist? Honestly, I can't imagine how Quartus would implement a tri-state driver without connecting the output enable. Can you?

[Altera_Forum]

I can easily imagine that some obscure command may be necessary to do this. And yes, looking at the netlist would probably clarify the issue.  

   --- Quote Start ---  Why don't you just implement a simple circuit and watch the results in the Quartus netlist? Honestly, I can't imagine how Quartus would implement a tri-state driver without connecting the output enable. Can you?  --- Quote End ---  

[Altera_Forum]

Correct, the netlist shows the assignment it done automatically.  

   --- Quote Start ---  Why don't you just implement a simple circuit and watch the results in the Quartus netlist? Honestly, I can't imagine how Quartus would implement a tri-state driver without connecting the output enable. Can you?  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  I can easily imagine that some obscure command may be necessary to do this.  --- Quote End ---   I can't remember needing obscure commands for standard logic functionality with Altera Quartus. May be for some very special one.