calculate needed set clock uncertainty from ppm

[Altera_Forum]

hi, 

 So have a 125mhz with ppm of 300, my calcualtions are:  300ppm is 0.03% of 8 ns -> 2.4ps ~3ps  so i had put on the SDC:   set_clock_uncertainty -rise_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -setup 0.003 set_clock_uncertainty -rise_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -setup 0.003  set_clock_uncertainty -fall_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -setup 0.003  set_clock_uncertainty -fall_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -setup 0.003    set_clock_uncertainty -rise_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -hold 0.003 set_clock_uncertainty -rise_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -hold 0.003  set_clock_uncertainty -fall_from [get_clocks {clk125}] -rise_to [get_clocks {clk125}] -hold 0.003  set_clock_uncertainty -fall_from [get_clocks {clk125}] -fall_to [get_clocks {clk125}] -hold 0.003          is that looks right?  or i should double the value?

[Altera_Forum]

That looks right to me. You don't need to double your values as this is handled in the separate entries for rise to rise etc. 

 However, these are pretty small numbers. I suggest you run the "derive_clock_uncertainty" for your design. This will add similar entries to the constraints file but knowing nothing of the quality of the clock you're using. These values will be based on the uncertainty introduced by the FPGA's buffers/routing etc. I suspect you'll find these number significantly larger than the 3ps you're proposing to add - e.g. I typically see 20ps for Cyclone IV devices. Needless to say (perhaps) you need to use the larger uncertainty figure.  Cheers, Alex