can any one help me in VHDL codes plz

Altera_Forum · ‎07-07-2011

Hi all ,

I wanna help to write these 2 codes of the VHDL on Quartus II programme:

1) a structural VHDL code of 1 to 8 Demultiplexers. with an

active low Enable signal using 1 to 2 Demultiplexer. [ use Generate

statement]

__________________________________________________ ____________

2)

a structure or behavior VHDL code of 5-bits binary

counter with a synchronous load signal to preset the counter to a

specific initial state. the output of the counter ( Q0 to Q4) are

connected to a binary decoder that shows the state of the counter.

In our college they did not teach us this programme and they want from us to make these codes in the next 3 days and really i am so poor in the programming, So can any one help me plz :cry:

Altera_Forum · ‎07-07-2011

Hi, are you french ;-) ?

--- Quote Start ---

In our college they did not teach us this programme and they want from us to make these codes in the next 3 days

--- Quote End ---

Did you go to the courses :-D ? Or your teacher is on hollydays.

VHDL is Very High frenquency Integrated Circuit Hardware description language.

So, you should have an "intro" to this language.

First, make schema (for beginners).

Second, describe it in VHDL

In Quartus, you have templates. You will find them in Quartus menu.

In the Word Wide Web (thanks to the billions of persons who are connected on and can help a poor lonesome student by freely sharing tons of knowledge....) , there are numerous examples.

Q1) Not easy for pure beginners

first make "n

active low Enable signal using 1 to 2 Demultiplexer"

Q2)

http://en.wikipedia.org/wiki/vhdl

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;    -- for the unsigned type
 
entity counter_example is
generic ( WIDTH : integer := 5); -- 5 here :-)
port (
  CLK, RESET, LOAD : in std_logic;
  DATA : in  unsigned(WIDTH-1 downto 0);  
  Q    : out unsigned(WIDTH-1 downto 0));
end entity counter_example;
 
architecture counter_example_a of counter_example is
signal cnt : unsigned(WIDTH-1 downto 0);
begin
  process(RESET, CLK) is
  begin
    if RESET = '1' then
      cnt <= (others => '0'); -- async load
    elsif rising_edge(CLK) then -- synchronous domain below
      if LOAD = '1' then
        cnt <= DATA; -- sync load
      else
        cnt <= cnt + 1;
      end if;
    end if;
  end process;
 
  Q <= cnt;
end architecture counter_example_a;

...

Good homeworks ! (in my opinon, this is the worst way to learn something)

And .......... Good Luck !

Altera_Forum · ‎07-08-2011

hi sir,

yes we took a quick intro and the teacher now is in holiday -_-

really thank you for that :)

Altera_Forum · ‎07-08-2011

one of my references : vhdl syntax : http://amouf.chez.com/syntaxe.htm with few examples

You don't need procedures and functions, neither package.