carry chain delay differs a lot between two LEs in same LAB

[BazingaWei]

I implemented TDC based on carry chain in Cyclone IV. By measuring the bin size based on code density method, after lots of random test, the delay destribution varies a lot for each delay element in the carry chain. Especially, the delays for two dalay elements(logic element)next to each other in same LAB differ a lot (see the figure). 

My question is: why most carry signal 'falls' in the odd-indexed position?

ths a lot!

 

[RichardTanSY_Intel · Accepted solution]

Perhaps the below article may help clarify your questions. 

https://arxiv.org/ftp/arxiv/papers/1805/1805.12390.pdf

[BazingaWei]

That is exactly what i want, thanks a lot