I implemented TDC based on carry chain in Cyclone IV. By measuring the bin size based on code density method, after lots of random test, the delay destribution varies a lot for each delay element in the carry chain. Especially, the delays for two dalay elements(logic element)next to each other in same LAB differ a lot (see the figure).
My question is: why most carry signal 'falls' in the odd-indexed position?
ths a lot!