- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
We have a EP3SE50-based design and we have found 3 failing boards out of 25 tested so far, where one of VCCA_PLL pins gets internally shorted after power up. In the design, all VCCA_PLL pins are powered up. What can possibly cause such damage? We have monitored ramp up of different FPGA voltages and they seem to be fine. Any advice? MandanaLink Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
shorts and opens are said to normally be electrical over stress:
http://www.altera.com/support/devices/dvs-failure_analysis.html
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page