change the langage of the Nios

[Altera_Forum]

Hi, 

 I work on an example project. The Nios was creating in verilog (so the toplevel is in verilog).   Do you know if there is an option for changing verilog in vhdl ? Or do you know a good translator (free software) : verilog -> vhdl ? So, I could use the example project and modify it because I don't know verilog.

[Altera_Forum]

With SOPC Builder closed, open the .sopc file for your project in a text editor and change the line: 

 <parameter valueString="VERILOG" name="hdlLanguage"/>  to:  <parameter valueString="VHDL" name="hdlLanguage"/>  next time you open the project in SOPC Builder it should generate the system in VHDL  I've not found a way of doing this through the GUI but I'm still using 7.2SP3 - later versions may have implemented this properly.

[Altera_Forum]

I work with the version 8.0 

 I found this (and modify) in the .sopc (I guess it's different because it's the version 8.0):   </parameter> <parameter name="deviceFamily" value="CYCLONEIII" /> <parameter name="generateLegacySim" value="false" /> <parameter name="hardcopyCompatible" value="false" /> <parameter name="hdlLanguage" value="VHDL" /> <parameter name="projectName">cycloneIII_3c25_niosII_standard.qpf</parameter> <parameter name="systemHash" value="35242142081" /> <parameter name="timeStamp" value="1214205055989" />   I generated the sopc builder and it generated the files .vhd  EXCEPT the file "name_sopc.vhd" where name_sopc is the name of your system sopc. So I don't have the toplevel. This change is not enough.

[Altera_Forum]

--- Quote Start ---  I work with the version 8.0   ...   I generated the sopc builder and it generated the files .vhd  EXCEPT the file "name_sopc.vhd" where name_sopc is the name of your system sopc. So I don't have the toplevel. This change is not enough.  --- Quote End ---    Someone using QII 8.0 SP1 told me that he changed from Verilog to VHDL for simulation by editing the hdlLanguage parameter.  As far as I know there is no officially supported way to change the SOPC Builder system language after the system is first created. Changing the language by modifying the hdlLanguage parameter in the .sopc file is a use-at-your-own-risk method. If it worked for the simulation file for the person I know though, I would expect it to work for all the HDL files generated by SOPC Builder for synthesis.     --- Quote Start ---  I've not found a way of doing this through the GUI but I'm still using 7.2SP3 - later versions may have implemented this properly.  --- Quote End ---    The tool supports making this choice only when the SOPC Builder system is first created. That's not a bug. It's similar to having to choose the MegaWizard variation file language up front when you first configure a megafunction with the MegaWizard.  It would be nice if the tool were enhanced to allow this though. You could file a service request to ask for this. If enough people ask for it, it might be done.

[Altera_Forum]

I am using quartus v9.1 and I found that changing "VERILOG" to 

"VHDL" in the .sopc file was not sufficient.  I had to find all of the references to "VERILOG" or "verilog" and  change them to "VHDL" or "vhdl" in the following files:  nios2.ptf nios2.ptf.8.0 nios2.ptf.bak nios2.ptf.pre_generation_ptf nios2.sopc nios2.sopcinfo sopcb_tb2_nios2.xml  Only then did sopc builder actually spit out a vhdl version of the system rather than a verilog one.  Imperative: Altera, add a small menu item to the sopc builder GUI that allows this to be changed at any time!

[Altera_Forum]

You should open a "Service Request" (bug report) in altera.com 

Altera emploeys do not read this forum

[Altera_Forum]

--- Quote Start ---  I am using quartus v9.1 and I found that changing "VERILOG" to "VHDL" in the .sopc file was not sufficient.  I had to find all of the references to "VERILOG" or "verilog" and  change them to "VHDL" or "vhdl" in the following files:  nios2.ptf nios2.ptf.8.0 nios2.ptf.bak nios2.ptf.pre_generation_ptf nios2.sopc nios2.sopcinfo sopcb_tb2_nios2.xml  Only then did sopc builder actually spit out a vhdl version of the system rather than a verilog one.  --- Quote End ---  All of the files you listed except the .sopc file are generated by SOPC builder. You can just change the reference in the .sopc file, delete the rest of them, then regenerate the system.