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hello,
someone has already used masterBlaster or usbBlaster? which of the two advised to me? thank you... Stefania:)Link Copied
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Hi Stefania,
You should use USB Blaster, especially if you work with QuartusII (in obsolete software MAX+PLUS II the USB Blaster is not supported). USB Blaster is newer hardware from Altera. MasterBlaster is older one. Also you can use cheapest clone of USB Blaster from Terasic. :)- Mark as New
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thank you...now I bore you again...
what are the differnce between Terasic ($50) and Altera ($300) USB BLASTER???? thanks..:)- Mark as New
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The main difference in avidity :)
Altera's USB Blaster has shielded printed flexible flat cable. Terasic's one has cheap ribbon cable. Altera's level translator based on AD3304 from AnalogDevices. Terasic's one based on PI3VT245 from Pericom. Alaso Terasic use more slow and more cheap CPLD (-10 speed grade, instead -4 in Altera's blaster).- Mark as New
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thanks...
:)- Mark as New
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You must use a usb blaster if you plan to use a stratix 2 or newer device (byteblaster cannot program it).
I had an issue with the Terasic blaster, when I leave it on the jtag socket, my fpga does not start, issue that I don't have with the altera usb blaser.- Mark as New
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--- Quote Start --- I had an issue with the Terasic blaster, when I leave it on the jtag socket, my fpga does not start, issue that I don't have with the altera usb blaser. --- Quote End --- That's interesting - we see the opposite behavior in active serial mode - with the Altera usb blaster, we have to disconnect it after programming; with the Terasic, we can leave it connected. Again, that's Active Serial mode. We use JTAG for Signaltap and nios2-gdb-server, but I never did try to get EPCS programming to work via JTAG. When we do use JTAG, I have never had a problem with the device not starting. We're using Stratix II. \chuck
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I also use active serial mode ;-)
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I use an USB-Blaster from Terasic.
When I program the EP2CS in active serial (Cyclone II on board) if I leave the connector, my FPGA doesn't leave the reset status. This is the only strange behavior. I use also in JTAG mode or with Signal Tap without problem. Never tried with an Altera USB-Blaster.- Mark as New
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--- Quote Start --- You must use a usb blaster if you plan to use a stratix 2 or newer device (byteblaster cannot program it). .... --- Quote End --- It is strange. I'm use Byteblaster2 for working with StratixII without any problem. --- Quote Start --- I had an issue with the Terasic blaster, then I leave it on the jtag socket, my fpga does not start....... --- Quote End --- May be this mean that PI3VT3245 does not swithch to high impedance state. You should check an Enable signal on the pin 19 of PI3VT3245. --- Quote Start --- ... - we see the opposite behavior in active serial mode - with the Altera usb blaster ... --- Quote End --- What is revision of your Altera USB Blaster? B or C? I have developed my own USB Blaster clone :) based on EPM240. It work properly in all modes :)
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excused my inexperience..if I understand correctly, when I mean program in JTAg mode, throught the follow signals:
1) nCE, nCEO, nSTATUS, CONF_DONE, nCONFIG, MSEL0, MSEL1, DATA0, DCLK, (form cyclone II to board) and 2) TCK,TDO,TMS,TDI (from USBBLASTER to cyclone II) I write my .sof file in "Serial flash loader" ?????????????????????? the result of my programmation is that when i leave Supply my fpga remain programmed because i have written in flash. It is correct??????????? thank you:) :) Stefania- Mark as New
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--- Quote Start --- It is correct??????????? Stefania --- Quote End --- Yes. Do you read application note 370 (http://http://www.altera.com/literature/an/an370.pdf) from Altera website? Proper schematic for using SFL and Cyclone/CycloneII is attached (sorry for russian comments on the picture :) ).
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Do you need create a nonvolatile application (i.e. program external serial configuration device with AS interface via JTAG interface)?
Or you need only configure FPGA via JTAG?- Mark as New
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Hello Stefania,
I'll try to help: There are two variants of JTAG programming discussed in here:- Volatile JTAG programming This kind of programming is commonly used for debugging purposes, when you want a fast programming of the device or use features like the Signal Tap Logic Analyzer. This file is commonly a so called *.sof file. After disconneting power, all configured data is lost.
- Nonvolatile JTAG programming of Active Serial Configuration Devices This kind of programming is used when you want to programm your active serial eeprom over JTAG. This is the case when you don't have the boardspace for an additional connector, or there are more than one device in your JTAG chain and want to configure them in one programming cycle. This is a typical production scenario. Then you will create a programming file with the boatloader for your fpga device and the configuration file for the eeprom. (Quartus II -> File -> Convert Programming File -> Generate *.jic File). After power on reset the Boatloader will disappear out of the FPGA and it is configured out of the active serial config prom
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i want a non volatile application.
if possible i want a non volatile application using only cyclone II usb blaster and quartus, without any others component. Stefania help me because now i'm confused..... :)- Mark as New
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Stefania, with USB Blaster you can use two ways :
1. with Active Serial interface : http://www.altera.com/literature/hb/cfg/cyc_c51014.pdf (http://www.altera.com/literature/hb/cfg/cyc_c51014.pdf), see page 4-9 (MSEL0 and MSEL1 have to be tied to ground for AS). It is the simplest way. SFL is not need but you have to add AS connector to your board. 2. with JTAG interface - in this case you have to use SFL, as described in AN370 (or look at Christian's note - it is very useful).- Mark as New
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sig sig
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Hi Stefania,
--- Quote Start --- i want a non volatile application. if possible i want a non volatile application using only cyclone II usb blaster and quartus, without any others component. --- Quote End --- in non volatile applications, you will always need some kind of configuration device when using SRAM based FPGAs (there are some other kinds of SRAM FPGAs out in the market wich have the config device in the package of the FPGA, but this is a minority of devices). This could be an SPI Flash (like AS Configuration) a microcontrolelr or paralleflash or whatever. So the minimal configuration you will need (if you want JTAG for debugging or other purposes) is the Cyclone II with JTAG Interface, the SPI Flash for Active serial Configuration attached to the CycloneII, USB-Blaster and Quartus II. Then the schematic will look like Stewart Little posted. I hope you are now a little bit less confused. :) Christian- Mark as New
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We use EPC64 devices to write the pof file using the usb blaster
in serial active mode for our Stratix 2 fpga's- Mark as New
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Hi all,
I would like to use a MASTERBLASTER to program a CPLD Max II. Programming operation will be in In-circuit test,soft HP-UX B 10.20. You have some advice for me? Thanks in advance, Marius
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