circumventing input output gates

[Altera_Forum]

I am developing asynchronous designs. This requires me to measure directly the voltage of specific logic gates on the FPGA. However, when I route signals out of the chip, they always go through I/O elements (IOEs), which change the voltage levels and control the slew rate. Are there outputs that are directly linked to the interconnect fabric without additional gates? In the Cyclone IV device handbook, I found the possibility to configure IOEs as Open-Drain Output, is that an option? 

 Thanks!

[Altera_Forum]

--- Quote Start ---  I am developing asynchronous designs. This requires me to measure directly the voltage of specific logic gates on the FPGA. However, when I route signals out of the chip, they always go through I/O elements (IOEs), which change the voltage levels and control the slew rate. Are there outputs that are directly linked to the interconnect fabric without additional gates? In the Cyclone IV device handbook, I found the possibility to configure IOEs as Open-Drain Output, is that an option?  Thanks!  --- Quote End ---    You need to be aware that there are no gates in the fabric, just LUTs. The open drain is still a feature of io as far as I am aware.