clkn input clock can not drive PLL on stratixII

[Altera_Forum]

I'm working on StratixII device, and in would like to inject a clock on the CLK9n input pin of my FPGA to drive a PLL. 

When looking at the Stratix II Device Handbook, it is possible to do that by inserting clock mux block (ALTCTRL) between the CLK9n input pin and the CLKIN input signal of the PLL.  But, QuartusII (9.1) stops the compilation process by an error message saying that Quartus can't place a fast or enhanced PLL in PLL location PLL_n due to device constraints..... See attached the message.  I tried with the CLK9p pin, and of course it works.  My question is simple : is it possible to drive a PLL by an input CLKn pin ? If yes, how to do that ?  Thanks.

[Altera_Forum]

I don't see anything in the user's guide that indicates the CLKn pins can drive the PLL inclk pins. In fact it looks to me like it has to be CLKp pin. 

 The only exception I can see is that some of the CLKn pins can drive the global clock network. But only the ones on the Top and Bottom of the devices. CLK9n is not one of these (see table 1-22) http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf  If you were using a CLKn pin listed in table 1-22 you could drive a global clock from that pin and then take the global clock as input to a PLL. It doesn't look like that's going to happen with CLK9n.  Jake

[Altera_Forum]

Hi Jake, 

 Thanks for your answer.