The clkp and clkn can be used to insert a differential clock signal into the FPGA. My question is, can we have 2 separate independent single ended clock signals being input into the FPGA on these two pins or just one single ended clock on either of them?
This question is specifically about MAX 10 and Cyclone 10 LP.
The different dedicated clock pins feed different GLCK networks. Is the fitter able to link different GCLK networks together so a single pin can feed the whole device? How does it achieve this?
Also, why does fitter allow user to use general purpose I/O pin to input a clock signal?
GCLK networks are capable driving the entire device. Please refer below documentations:
MAX 10 GCLK network:
Cyclone 10 LP GCLK network: