clock control signal problem on Cyclone V GT

[verna]

I'm working with the Cyclone V GT development board.My design only needs to use frequency divider to get the signal, I tried to use 240MHz to divide the frequency and can get the signal successfully, instructed to change the input signal to be above 300MHz or 200MHz to divide the frequency, but I couldn't get the signal successfully. These are all within the control range of the crystal oscillator.

[SyafieqS]

Hi Chuang,

Are you using a custom code clock divider or clock enable signal for this? You should use clock enable signal and refer to below link related to the implementation.

https://www.intel.com/content/www/us/en/docs/programmable/683375/current/clock-enable-signals.html

[SyafieqS]

Hi Chuang,

May I know if there is any update?

[verna]

Hi SyafieqS,

Sorry,I still don't understand how to use it.

My project use Cyclone V GT REFCLK_QL3_P (X4) to input clock, because I use three ports to output one is on Cyclone V GT SMA_CLKOUT and the other use Terasic XTS-HSMC  (HSMB_CLK_OUT_P2 and HSMB_CLK_OUT_N2).

[verna]

Hi, SyafieqS

I tried the following method but it didn't work.

I try to use Clock Control Block (ALTCLKCTRL) to wire my input port and output port wire my counter to divide use three port pin outputs, my output ports one of which is SMA_CLKOUT on cyclone v gt and the other two pin outputs of Terasic XTS-HSMC, so I use REFCLK_QL3_P of HSMC port B connected to the clock input pin.

[SyafieqS]

Hi Chuang,

Is there any warning/error using the clock control block as suggested as you mentioned not able to do so?

Or still not manage to achieve the frequency desire?

[SyafieqS]

Chuang,

May I know if there is any update?

[verna]

Hi SyafieqS,

I still not solve this problem. There's not error suggest. The clock control block warning suggest is Warning (15846): ena port of Clock Buffer Block "ALTCLK_altclkctrl_9kh:ALTCLK_altclkctrl_9kh_component|sd1" is connected to GND.

[SyafieqS]

Hi Chuang,

I found some discussion might be useful related to clock divider.

Please take a look

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Best-way-to-code-a-clock-divider/td-p/123104

[SyafieqS]

Let me know any update on this

[verna]

Hi SyafieqS,

I will try this method. If this method is still unsuccessful, I may only use frequencies between 200MHz and 300MHz for frequency division, and I can only temporarily not use other frequencies for frequency division.

 Thank you tour suggest.

[SyafieqS]

Understood. Let me know if there is any other concern at our end.