clock gating in FPGA

[Altera_Forum]

Hi, 

 I want to do clock gating in a design targetted for FPGA. The design was intially build for ASIC which have custom clock gating cells (latch based). I need to synthesize this design in Altera Stratix FPGA.  Should i replace this clock gating cells with FPGA clock gating cells. If yes, please let me know how to take this forward.  Regards, freak

[Altera_Forum]

Yes, you should. 

 In Altera FPGAs, use a ALT_CLKCTRL block for clock gating or clock multiplexing.

[Altera_Forum]

Hi, 

 Thanks for the reply. Can you please share the rtl, or please let me know from where can i get this code.  Regards, Jaseel

[Altera_Forum]

Just check the user guide 

 http://www.altera.com/literature/ug/ug_altclock.pdf