code is simple, error is hard to understand

[Altera_Forum]

excuse me, i m a beginner, so the question may be meaningless. 

 I SIMPLY WROTE MY CODE LIKE:     process(a_in , clk) begin   if clk'event and clk='1' then c_out<=a_in; else c_out<='0'; end if;   end process;       then i met the error like this&#65306;&#65282;Can't infer register for 'c_out' at test.vhd(20) because it does not hold its value outside the clock edge".   i think i have wrote "else c_out<=' 0'; " why Quartus II still says it does not hold its value outside the clock edge?   WHEN I CHANGE THE CODE TO:    c_out <= a_in;    if clk'event and clk='1' then c_out<=a_in; end if;   IT DOESN'T REPORT ANY ERRORS.   BUT WHEN IT IS   c_out <= '1';   if clk'event and clk='1' then c_out<=a_in; end if;   THE SAME ERROR OCCURS.   so, could anyone give some help?

[Altera_Forum]

--- Quote Start ---  excuse me, i m a beginner, so the question may be meaningless.   I SIMPLY WROTE MY CODE LIKE:     process(a_in , clk) begin   if clk'event and clk='1' then c_out<=a_in; else c_out<='0'; end if;   end process;     then i met the error like this&#65306;&#65282;Can't infer register for 'c_out' at test.vhd(20) because it does not hold its value outside the clock edge".   i think i have wrote "else c_out<=' 0'; " why Quartus II still says it does not hold its value outside the clock edge?   WHEN I CHANGE THE CODE TO:    c_out <= a_in;    if clk'event and clk='1' then c_out<=a_in; end if;   IT DOESN'T REPORT ANY ERRORS.   BUT WHEN IT IS   c_out <= '1';   if clk'event and clk='1' then c_out<=a_in; end if;   THE SAME ERROR OCCURS.   so, could anyone give some help?  --- Quote End ---     Hi,  in your code you define a register which is sensitive to the rising clock edge. With the rising edge the register will store the value of the input a_in. The output of a register could only change at the active edge ( in your case the rising edge). The only possible else branch is "else c_out <= c_out;" which means store the value until the next rising clock edge.  Kind regards  GPK

[Altera_Forum]

The way you have written the code that gives the error, you are asking the synthesisor to produce a circuit that registers a_in for the really tiny amount of time that encompasses the rising edge. As soon as the clock is at '1', you're trying to force the output to '0'. 

 You should never put an else case on a clock if. And you should never assign a signal inside and outside the clock branch.

[Altera_Forum]

I really appreciate your explaination, pletz and Tricky . I may still have some habbit of using C language, so, if...else..seems absolutely right to me.

[Altera_Forum]

With HDLs, you have to forget about the language, and think about the hardware.

[Altera_Forum]

Please remove a_in from the sensitivity list. It's confusing the compiler.