comparator

[Altera_Forum]

i need to do  

Greater or equal than  Less or Equal than  not equal   but it is not working with me  could you check this code i have done greater or equal than but it is not workin but aeqb,agtb,altb are working correctly  library ieee; USE ieee.std_logic_1164.ALL; entity compare8 is port( a,b : IN INTEGER RANGE 0 to 255; agtb,aeqb,altb,ageqb : OUT STD_LOGIC ); end compare8; architecture a of compare8 is SIGNAL compare : STD_LOGIC_VECTOR (3 downto 0); BEGIN process(a,b) BEGIN if a > b THEN compare <= "1110"; ELSIF a < b THEN compare <= "1101"; ELSIF a = b THEN compare <= "1011"; ELSIF ( a >= b ) THEN compare <= "0111"; ELSE compare <= "1111"; END IF; END PROCESS; agtb <= compare(0); altb <= compare(1); aeqb <= compare(2); ageqb <= compare(3); end a;

[Altera_Forum]

if a > b THEN compare <= "1110"; ELSIF a < b THEN compare <= "1101"; ELSIF a = b THEN compare <= "1011"; ELSIF ( a >= b ) THEN compare <= "0111"; ELSE compare <= "1111"; END IF;The conditions in an IF statements are evaluated in order. The ">=" case in your code will never trigger as in that case either ">" or "=" will always be evaluated first.

[Altera_Forum]

so how can i use greater or equal than  

could you check this page please http://eesun.free.fr/doc/vhdlref/refguide/language_overview/objects__data_types_and_operators/vhdl_operators.htm

[Altera_Forum]

--- Quote Start ---   The ">=" case in your code will never trigger as in that case either ">" or "=" will always be evaluated first.  --- Quote End ---    could you explain more what u mean by this, sorry ican't understand what u mean exactly

[Altera_Forum]

Hi Fedail, 

Why not making this way?   process(a,b) BEGIN IF (a < b) THEN altb <= "1"; ageqb <= "0"; agtb >= "0"; aeqb <= "0"; ELSIF(a = b) THEN altb <= "0"; ageqb <= "1"; agtb >= "0"; aeqb <= "1"; ELSE altb <= "0"; ageqb <= "1"; agtb >= "1"; aeqb <= "0"; END IF; END   Regards

[Altera_Forum]

--- Quote Start ---  could you explain more what u mean by this, sorry ican't understand what u mean exactly  --- Quote End ---    All if/elsif/else paths are mutually exclusive. Because ">=" will also trigger the ">" or the "=" branch, you will never end up in the ">=" branch. You can only go down 1 branch.

[Altera_Forum]

aha i got it  

i'll try another way

[Altera_Forum]

i solve the problem wih other way  

 if a > b THEN compare <= "010110"; ELSIF a < b THEN compare <= "001101"; ELSIF a = b THEN compare <= "100011"; ELSE compare <= "111111"; END IF; END PROCESS; agtb <= compare(0); altb <= compare(1); aeqb <= compare(2); ageqb <= compare(3); aleqb <= compare(4); anotb <= compare(5);   put could you check this image please why this happened with me i mean this small spike http://i25.tinypic.com/hreuzo.png

[Altera_Forum]

could anyone help me with this please

[Altera_Forum]

because you havent synchronised it.

[Altera_Forum]

Fedail, 

 the glitches in the output occur because your design is purely combinatorial. Changes of input signals have different paths to the output, hence the glitches.   --- Quote Start ---  Tricky:  because you havent synchronised it.  --- Quote End ---   If you register the outputs you will not have those glitches anymore. But now beware of setup times ...

[Altera_Forum]

which one should i synchronised and how

[Altera_Forum]

This is rather basic knowledge, but I'll humour you. 

You might invest in a few good books on VHDL, I suggest you get a copy of: Circuit Design with VHDL by Volnei A. Pedroni ISBN 978-0-262-16224-1 process( Clk ) begin if rising_edge( Clk ) then IF a > b THEN compare <= "010110"; ELSIF a < b THEN compare <= "001101"; ELSIF a = b THEN compare <= "100011"; ELSE compare <= "111111"; END IF; end if ; END PROCESS;

[Altera_Forum]

very thanks i am still learning with some book for DUECK