concatenation on wire

[Altera_Forum]

Hi all, 

 I did a simple experiments regarding concatenation on wire, below is the verilog code.  // file : le_count_experiment.v // date : 17 dec 2010 // author : ty6 // to experiment le count of various operator module le_count_experiment (//input  in1,  in2,  out,    clk,  ld,  rst); //parameter parameter data_width = 4;  //input input [data_width-1:0] in1; input [data_width-1:0] in2; input clk; input rst; input ld;  //output output [data_width-1:0] out;  //wire wire [9*data_width-1:0] reg_in/* synthesis keep */; wire [9*data_width-1:0] reg_out/* synthesis keep */;  //assigment assign reg_in = {in1, in2}; assign out = reg_out[data_width-1:0];  regn register (.d(reg_in),   .clk(clk),   .en(ld),   .rst(rst),   .q(reg_out));  defparam register.data_width = 9*data_width;  endmodule   I define reg_in as wire (9*4 = 36 bits) and concatenate both inputs in1 and in2 (both 4 bits) to become 8bits. However, i got a compilation warning: warning: design contains 4 input pin(s) that do not drive logic  warning (15610): no output dependent on input pin "in1[0]"  warning (15610): no output dependent on input pin "in1[1]"  warning (15610): no output dependent on input pin "in1[2]"  warning (15610): no output dependent on input pin "in1[3]"  and the simulation result shows that only in2 is assigned to reg_in, and reg_in is only 4bits wire in simulation.  Anyone has any idea why concatenation on wire does not work?  Thanks and Regards, ty6

[Altera_Forum]

assign reg_in = {in1, in2}; 

I would expect a compilation error, because the expression width doesn't match in assignment of reg_in. I'm not sure, if you can expect a particular result in case of an illegal assignment.

[Altera_Forum]

means that reg_in, in1 and in2 must be same width?

[Altera_Forum]

--- Quote Start ---  means that reg_in, in1 and in2 must be same width?  --- Quote End ---   No it's not required. I thought, it would be the case, because VHDL wouldn't allow this assignment, Verilog however does. But the explanation is much easier. In1 is simply assigned to the part of reg_in, that's never read. You have to double the width of reg_out to see the in1 data.   I'm not absolutely sure, if you know, what a concatenation is? With DATA_WIDTH = 4, it creates a bit-vector of length 8. If you only read the lower 4 bits, in1 is ignored.

[Altera_Forum]

Here's an example, lets say we had this: 

 wire A, B, C, D; wire [3:0] aBUS;  assign A = 1'b1; assign B = 1'b1; assign C = 1'b0; assign D = 1'b1;  assign aBUS = {A, B, C, D};  The signal "aBUS" would have the value 4'b1101 fed into it. In other words the width of the concatenated signal is the sum of the widths of all the signals you are concatenating.

[Altera_Forum]

Hey FvM, you are right, it just read lower 4 bits. Therefore upper 4 bits, in1 are ignored. 

 Thanks

[Altera_Forum]

There is nothing wrong with the result. 

If you trace the path in reverse order. out is 4 bit thus it can take only 4 bits as an input, source to out is 36 bit from reg_in but it will take only least significant 4 bits. The reg_in gets 8 bits as an input but final o/p is only 4 bit reaching to the port thus compiler removes upper 4 bits and leaves only lsb 4 bits , i.e. in2.  Thus in1 is reported to be removed, since it doesnt drive any logic.