config_done pin is drived down again after download

[Altera_Forum]

Hi, everybody  

I can configurate my device(EP3C) with JTAG programmer successfully. It indicates in quartus2 that it can access to JTAG successfully. Also, config_done pin can be drive to high after downlaod. And I can detect signals normally. However, few seconds later, config_done will be down and all the I/O pins are tri-state. I think it means that FPGA lose code again. is it casued by unstability of supply power?  What's more, I don't insert two 25 ohm serial resisters near TDO and TDI pins as recommend in datasheet. Can it be the reason of my problem?

[Altera_Forum]

Is the working time constant or random, I mean between configuration done and configuration lost? 

Does your design contain some particular features, like remote update or any security check device?

[Altera_Forum]

--- Quote Start ---  Is the working time constant or random, I mean between configuration done and configuration lost? Does your design contain some particular features, like remote update or any security check device?  --- Quote End ---   I try it again this afternoon, it seems that device could work normally now. I don't change any in my design. Under this situation, I don't know whether it is stable to use. I think the working time is random. And it can only last few seconds this before. Besides this, I don't use remote update or security check device in my design.