Hi,I'm using de-10 standard and I need to connect RX and TX signals to UART, but i need them to connect to FPGA. I know you can connect hps to fpga, but I cannot find any examples for my case. How do I connect them if I only need UART-to-USB bridge? Thanks
Hi, I assume your IP is in the FPGA logic, and that this IP will output info via UART protocol to the external world. In this case, you can route the UART IP to the FPGA I/O that is located in the DE10- standard GPIO expansion header, and connect the external two pins (TX, RX) externally.
Hi, your assumptions are correct, but the thing is, my boss specially wants to transfer data using UART-to-USB, so I have no other choice here really, that's why I'm asking about thatThanks anyway)
You can utilize the HPS's UART, but it is a bit more complicated. Firstly, you need to open Qsys, set the two UART pins as loan I/O to the FPGA. Qsys will identify these as 67 I/O channels exported to the FPGA (even though only two of them are) so you need to count the channel numbers correctly. Then, assuming that the FPGA IP has it's own enable signals, you can connect that IP's output to these two HPS Pins that are used as loan I/O.Finally, you will have to compile the design, update the preloader to the HPS SD Card (the preloader sets the HPS I/O properties, including the loan I/O settings) and hopefully it works :) (it's complicated, really. If you have $60 perhaps you can consider this: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=225&no=1025&partno=1. Personally I'll solder the 2 wires out :))
Sorry, but I have an additional question, I need to set BOTH UART pins to FPGA? Shouldn't I set one of them as HPS I/O? And what exactly is a loan IO? (Sorry, I'm new to this, that's why I'm asking)
Loan I/O means that the HPS's own (dedicated I/O) are "loaned" to the FPGA fabric. In this way, externally the pins are connected to the UART-USB converter, but they are routed to the FPGA logic (instead of the HPS's UART controller) - do note that their mux and I/O settings are stilled controlled by the HPS, hence the need for the updated preloader.I assume that your FPGA IP requires both RX and TX, hence the suggestion to set both I/Os as loan IO. Try looking at this example here: https://www.youtube.com/watch?v=crwzmsj1jkg