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I'm using DDR2 ICs without any impedance control at all, you just need to keep the IC very close to the FPGA, my longest trace is about 0.4". The only one that you do really need is the 100R differential termination on the CLK+/- pair. Obviously you can only have one IC per bus. I have one on the top bus and one on the bottom bus of a Cyclone III, and have tested thoroughly with a ep3c40 and ep3c16 at 165MHz.
Definately not. There are very strict rules about where the DQ and DQS pins can be located. You definately need to read the documents, try out a layout and get it to compile before making your PCB. If you haven't put the ram connections in the exact right place it won't work.
