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Beginner
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constraints on output clock

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My question is about how to generate a 40MHz clock from MAX10 as a clock source for another chip on PCB.

What I have done is implementing a PLL with external 20Mhz crystal as the input and output c0 is configured to 40MHz. What I'm going to do is to connect this 40MHz pin to the clock port of another chip(CY7c68013).

My question is:

1 .  Can I  assign any pin on MAX10 with PLL output c0 as output clock? Or I can only assign them to specific pins?

2. How would  I add timing constraints on this output pin?

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Moderator
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create_clock -name {clk_20M} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk_20M}]
derive_pll_clocks
create_generated_clock -source [get_pins <pll output pin>] -multiply_by 1 [get_ports clk_out_40M]
set_false_path -from [get_pins <pll output pin>] -to [get_ports clk_out_40M]

Your first and second constraints are correct.  The third constraint turns the path from the output pin of the PLL into a clock path since the timing analyzer assumes that device outputs are data paths, not clock paths.  I'm guessing your output port is named clk_out_40M but fix it if it is not.  For the PLL output pin name, you'll need to get that from a timing report or using the Name Finder.

For the final timing exception, you're indicating that the output path should not be analyzed for data since it is a clock path.  Again, set the PLL output pin name correctly.  And I switched the -to to point to the output port again. 

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3 Replies
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Moderator
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1) Yes.  You should be able to use any pin for output.

2) Here are the constraints you need in your .sdc: 1) base 20 MHz clock coming into device (create_clock), 2) generated 40 MHz clock on output of PLL (create_generated_clock or derive_pll_clocks), 3) second generated clock targeted to the output clock port with source as output pin of PLL and relationship to the source set to something like -multiply_by 1 (create_generated_clock), 4) false path to output port (set_false_path).

Reply if you need assistance with this.

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Beginner
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Thanks for your answer. I'm not quite sure about the 3rd constraint in your answer, so more explanation is appreciated.

I've listed the related code below.

This is PLL implementation, clk_out_40M is connected to a pin directly.

PLL inst_PLL (
	.areset(rst_n), 
	.inclk0(clk_20M), 
	.c0(clk_out_40M), 
	.locked()
	);

This is constraints in .sdc

create_clock -name {clk_20M} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk_20M}]
derive_pll_clocks
set_false_path -from [get_clocks clk_20M] -to [get_clocks clk_out_40M]

 

What I can't quite understand is why should I add "create_generated_clock -multiply_by 1"? I think "derive_pll_clocks" in my .sdc file has already told the tool relation between clk_20M and clk_out_40M?

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Moderator
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Close:

create_clock -name {clk_20M} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk_20M}]
derive_pll_clocks
create_generated_clock -source [get_pins <pll output pin>] -multiply_by 1 [get_ports clk_out_40M]
set_false_path -from [get_pins <pll output pin>] -to [get_ports clk_out_40M]

Your first and second constraints are correct.  The third constraint turns the path from the output pin of the PLL into a clock path since the timing analyzer assumes that device outputs are data paths, not clock paths.  I'm guessing your output port is named clk_out_40M but fix it if it is not.  For the PLL output pin name, you'll need to get that from a timing report or using the Name Finder.

For the final timing exception, you're indicating that the output path should not be analyzed for data since it is a clock path.  Again, set the PLL output pin name correctly.  And I switched the -to to point to the output port again. 

View solution in original post

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