create_generated_clock on multiple signals

[Altera_Forum]

I have a large array of DDR outputs that are being used as clocks. I'm following an example from AN433.pdf, though the document describes the constraint for only a single clock. How can I do this multiple times without typing out every single element? For example, is there a way to simplify this: 

 create_generated_clock -name output_clock_0 -source \[get_pins DDR|ddio_outa[0]|muxsel] [get_ports clk_out] create_generated_clock -name output_clock_1 -source \ [get_pins DDR|ddio_outa[1]|muxsel] [get_ports clk_out] create_generated_clock -name output_clock_2 -source \ [get_pins DDR|ddio_outa[2]|muxsel] [get_ports clk_out] ... create_generated_clock -name output_clock_59 -source \ [get_pins DDR|ddio_outa[59]|muxsel] [get_ports clk_out]   It seems like there should be a something like a for loop like this (excuse the psuedo-code):  for i in xrange(60):  create_generated_clock -name output_clock_{i} -source \ [get_pins DDR|ddio_outa[i]|muxsel] [get_ports clk_out]

[Altera_Forum]

SDC is Tcl, so you can use any Tcl constructs, like loops, to create constraints. See this page on Tcl I use as a reference all the time: 

 http://tmml.sourceforge.net/doc/tcl/

[Altera_Forum]

Thanks sstrell! a TCL loop was indeed the answer. I did have a hard time with a few of the characters in the create_generated_clock constraint which prevented the loop variable from being inserted properly. I ended up having to create full strings and inserting them as variables in the constraint. Here was my solution for others to view: 

 for {set x 0} {$x < 60} {incr x} {  set PA_SCLK_source "{u_top_SOPC|the_core_$x|core_$x|clkGen_DDR_out_inst|ALTDDIO_OUT_component|auto_generated|ddio_outa[0]|muxsel}"  set PA_SCL_pins "{PA_SCLK[$x]}"  create_generated_clock -name PA_SCLK_$x -source [get_pins $PA_SCLK_source] [get_ports $PA_SCL_pins] }  This created 60 instances of the following with reference numbers incrementing (0-59):  create_generated_clock -name PA_SCLK_0 -source [get_pins {u_top_SOPC|the_core_0|core_0|clkGen_DDR_out_inst|ALTDDIO_OUT_component|auto_generated|ddio_outa[0]|muxsel}] [get_ports {PA_SCLK[0]}]