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Altera_Forum
Honored Contributor I
781 Views

cyclon does not load

HI, 

I have an architecture with: 

- cyclon iv ep4ce6e22c8n with a programming chip epc64n 

it is a new release of an old schematic working fine, just the PCB was changed. 

I am able to load with byteblaster the programming chip but the fpga does not start. 

 

is the some one ableto help me? 

 

than you in advance, please find attached the photos of signal and schematic
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6 Replies
Altera_Forum
Honored Contributor I
43 Views

Why are you using 1K pullups to VCC (+3.3V?) on CONF_DONE, nCONFIG, and nSTATUS signals? Altera recommendation is 10K. 

 

1K pulldown on nCE should be OK. 

 

"it is a new release of an old schematic working fine, just the PCB was changed." ... it could also then be poor layout practices on the associated signals (DCLK, etc).
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

Why are you using 1K pullups to VCC (+3.3V?) on CONF_DONE, nCONFIG, and nSTATUS signals? Altera recommendation is 10K. 

 

1K pulldown on nCE should be OK. 

 

"it is a new release of an old schematic working fine, just the PCB was changed." ... it could also then be poor layout practices on the associated signals (DCLK, etc). 

--- Quote End ---  

 

 

HI 

thank you for the answer, I will ty 

 

thank you 

maurizio
Altera_Forum
Honored Contributor I
43 Views

HI, 

I changed the pull-up and down with 10Kohm resistor. 

nothing is changed. 

 

please let me suggest more 

mauriio stefani
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

HI, 

I changed the pull-up and down with 10Kohm resistor. 

nothing is changed. 

 

please let me suggest more 

mauriio stefani 

--- Quote End ---  

 

 

What about the MSEL[2:0] lines? You show both a 4.7K pullup to VCC and a pulldown to GND on each line. Obviously only one resistor of the pair should be populated per line. 

So what is the resistor stuffing selection on your MSEL[2:0] lines? For AS at 3.3V MSEL[2:0] should be either hi/lo/hi or lo/hi/lo depending on fast or standard POR.
Altera_Forum
Honored Contributor I
43 Views

HI, 

thank you for reply, 

the MSEL lines are wired to value of 2, means R42 mounted with value of "0" ohm, R39 mounted with value of "0" ohm, R30 mounted @0hm, R41, R29 and R40 are absent-. 

 

thank you, please help with any other suggestions 

thank you 

maurizio stefani
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

HI, 

thank you for reply, 

the MSEL lines are wired to value of 2, means R42 mounted with value of "0" ohm, R39 mounted with value of "0" ohm, R30 mounted @0hm, R41, R29 and R40 are absent-. 

 

thank you, please help with any other suggestions 

thank you 

maurizio stefani 

--- Quote End ---  

 

 

That should work. I would then check that the power supply power up meets the FPGA specs (ie, power supply sequencing, ramp rates are as required). I would also check for any unintended PCB solder shorts on the FPGA device. Do you have another board, and if so does it behave identically? 

 

Your signal waveforms as shown in your first post show a substantial amount of noise. It could be real, or it could be due to how your probes are attached. It would be interesting to see the DCLK and DATA waveforms at a more expanded scale (ie, higher horizontal resolution).
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