cyclone III configuration error when using epcs64

[Altera_Forum]

HI, I have meet a cyclone III configuration problem in this days, my development board is done by myself and using an epcs64 configuration chip and altera's EP3C40F484C8 chip, when I want jic files downloaded through the JTAG port to the epcs64 ,at the time of download progress bar reaches 85% , then failed. Information Tip "can't recognize silicon ID, operation failed"; I do not know what reason, I used the schematic configuration of the altera company's official documents (configuration handlebook) of "combining JTAG and AS configuration Schemes"; when I use AS download mode, the pof file can be downloadable, but it can not be read out;  

why? Is the epcs64 far away from the cyclone III when wiring?

[Altera_Forum]

I suspect a hardware JTAG problem. Do you have an oscilloscope you can use to look at the JTAG signals? 

 Jake

[Altera_Forum]

The pof “can not be read out”， so can the board run with this pof?!

[Altera_Forum]

--- Quote Start ---  The pof “can not be read out”， so can the board run with this pof?!  --- Quote End ---   thank you,I mean the pof file can be downloadable in AS mode ,but the cyclone III can't work by reading the epcs64 after restarting power supply.

[Altera_Forum]

--- Quote Start ---  I suspect a hardware JTAG problem. Do you have an oscilloscope you can use to look at the JTAG signals?   Jake  --- Quote End ---  thank you ,I think there is no problem in hardware JTAG,because the sof file can be downloaded into the cyclone III,and it work normally ,but you know the program is lost after restarting the power supply.

[Altera_Forum]

--- Quote Start ---  thank you,I mean the pof file can be downloadable in AS mode ,but the cyclone III can't work by reading the epcs64 after restarting power supply.  --- Quote End ---     What I mean is that can your board( or your FPGA) run after pof being downloaded?   You pointed that your jtag is ok in your last post, so if your fpga can't run with your pof, you should double check the interface between EPCS and fpga. You know the jic file is downloaded thru the jtag and a "bridge" between epcs64 and fpga, you must confirm that the jtag and the bridge should be both ok.   So if your fpga can run with pof, the "bridge" interface should be ok. pls check the interface between the epcs64 and fpga firstly.

[Altera_Forum]

--- Quote Start ---  What I mean is that can your board( or your FPGA) run after pof being downloaded?   You pointed that your jtag is ok in your last post, so if your fpga can't run with your pof, you should double check the interface between EPCS and fpga. You know the jic file is downloaded thru the jtag and a "bridge" between epcs64 and fpga, you must confirm that the jtag and the bridge should be both ok.   So if your fpga can run with pof, the "bridge" interface should be ok. pls check the interface between the epcs64 and fpga firstly.  --- Quote End ---   thanks,the fpga can't run with pof file. I also suspect the interface between epcs64 and fpga is not ok,but the board has been finished and can't be changed easily. so whether the epcs64 is away from fpga when wiring? can this condition result in the epcs64 can't be read normally by fpga?

[Altera_Forum]

My comments are below: 

1, Check your board and confirm that if the AS interafce is correct or not; 2, Check the pull-up resistor of the configuration circuit, 3, Monitor the configuration signals when power up.