cyclone IV ddr2 controller pin assignment problem

Altera_Forum · ‎03-19-2014

Error (169223): Can't place VREF pin AB4 (VREFGROUP_B3_N2) for pin mem_dq_bo of type bi-directional with SSTL-18 Class I I/O standard at location V8

        Error (169224): Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin AB4 (VREFGROUP_B3_N2) is used on device EP4CE40F23C8 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
            Info (169220): Location T8 (pad PAD_166): Pin oe of type output uses SSTL-18 Class I I/O standard
            Info (169220): Location T9 (pad PAD_167): Pin mem_cke_bo of type output uses SSTL-18 Class I I/O standard
            Info (169220): Location W7 (pad PAD_168): Pin od of type output uses SSTL-18 Class I I/O standard
            Info (169220): Location T10 (pad PAD_176): Pin mem_ras_n_bo of type output uses SSTL-18 Class I I/O standard
            Info (169220): Location T11 (pad PAD_177): Pin mem_ras_n_to of type output uses SSTL-18 Class I I/O standard
            Info (169225): Following 1 pins have the same output enable group -27: 1 pins require VREF pin and 1 pins could be output
                Info (169220): Location Y7 (pad PAD_169): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
            Info (169225): Following 1 pins have the same output enable group -26: 1 pins require VREF pin and 1 pins could be output
                Info (169220): Location W8 (pad PAD_172): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
            Info (169225): Following 1 pins have the same output enable group -25: 1 pins require VREF pin and 1 pins could be output
                Info (169220): Location AA7 (pad PAD_173): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
            Info (169225): Following 1 pins have the same output enable group -24: 1 pins require VREF pin and 1 pins could be output
                Info (169220): Location AB7 (pad PAD_174): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
            Info (169225): Following 1 pins have the same output enable group -23: 1 pins require VREF pin and 1 pins could be output
                Info (169220): Location Y8 (pad PAD_175): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
            Info (169222): Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
                Info (169220): Location T8 (pad PAD_166): Pin oe of type output uses SSTL-18 Class I I/O standard
                Info (169220): Location T9 (pad PAD_167): Pin mem_cke_bo of type output uses SSTL-18 Class I I/O standard
                Info (169220): Location W7 (pad PAD_168): Pin od of type output uses SSTL-18 Class I I/O standard
                Info (169220): Location Y7 (pad PAD_169): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
                Info (169221): Location U9 (pad PAD_170): unused (but has pin assignment of mem_dq_bo)
                Info (169221): Location V8 (pad PAD_171): unused (but has pin assignment of mem_dq_bo)
                Info (169220): Location W8 (pad PAD_172): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
                Info (169220): Location AA7 (pad PAD_173): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
                Info (169220): Location AB7 (pad PAD_174): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
                Info (169220): Location Y8 (pad PAD_175): Pin mem_dq_bo of type bi-directional uses SSTL-18 Class I I/O standard
                Info (169220): Location T10 (pad PAD_176): Pin mem_ras_n_bo of type output uses SSTL-18 Class I I/O standard
                Info (169220): Location T11 (pad PAD_177): Pin mem_ras_n_to of type output uses SSTL-18 Class I I/O standard

1,My project has two ddr2 controller(ALTMEMPHY IP),Full Compilation was unsuccessful ,the error is shown above .

So I move out some of pin in vrefgroup_b3_n2 to another vref groups and Full Compilation successful.

my problem is there are no enough pin for my project,and i wonder wheathe i can place some pin to vrefgroup_b3_n2 without compile error

I found the link about output enable group:http://www.alteraforum.com/forum/showthread.php?t=114

But I don't konw how to setting

please help me !

Altera_Forum · ‎03-23-2014

any one help??