cyclone v altera_pll warning

[Altera_Forum]

Hi Dears: 

 Below is the warning info:  Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y22_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks  Info (177008): PLL Sync:C_Sync|Mult1:\DontUseCodirPhyClock:Stage3|Mult1_0002:mult1_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL   I am using cyclone v e, and implemented PLLs in my project. The FPGA's input clock is 125Mhz, which input to the first PLL. The first PLL's outputs are 125mhz with o deg phase shift , 125mhz with 195 deg phase shift, 25.0 with 0 phase shift , 12.5 with -18 phase shift and 125 with -105 phase shift . all the out put move to a sync block which again is fed into differenct block. thanks