cyclone3 nstatus pin keeps dropping low

[Altera_Forum]

Hi, all. 

 My EP3C40Q240C8N can't work, and I found its nstatus pin would drop to low intermittently after board powered. there is no blaster down-loader, and nconfig pin keeps high. (waveform is shown in attatchment.)  is that mean my device is keeps on resting timely, and is it caused by power supply? All vccint and vcca are checked alright.  I'm totally confused. could anyone give me some hints?  Thanks a lot.

[Altera_Forum]

It looks like normal operation, e.g. when the FPGA is connected to serial configuration memory that doesn't hold a valid configuration. Yo didn't mention the inmplemented configuration scheme, however.

[Altera_Forum]

Hi, FvM, thank you very much for your reply when I'm worrying about this all day. 

 You mean this is normal? Actually, this is my second version board. The previous one works well, and nstatus pin always high when power on but not configure it yet. (this is the only difference between twos).   By handbook, the only reason could cause nstatus drops low seems to be low nconfig or monitored power. because there is no blaster installed yet, of course no configuration start yet. so nconfig pin is checked high. For this reason I guess there is some problem in power supply. However, power is alright too. (1.2v, 2.5v, 3.3v)  Power condition is checked with scope, and every related pin is alright. I tried to replace the power filter capacitors (from about 50uf to 200 uf), but no help.  My configuration are jtag and AS. I compare my schematic to handbook, but no difference found. The serial configuration device is EPCS16 and EEPROM DS28E01P-100. Specification is shown in attachment.  Actually, I don't think there is any problem with schematic, because previous board works well. But the board made after that all have the problem I mentioned. I want to find out the reason.  Thank you very much. 

[Altera_Forum]

If I understand right, you didn't yet try to configure the FPGAs. Failure of configuration would be an actual problem. Please notice, that in some situations the Quartus programmer option to disable the on-chip configuration controller must be set to allow intended JTAG actions when the AS flash is empty.

[Altera_Forum]

No, I used to try to configure the device. I can get config done signal with Jtag scheme, and AS scheme is normal too, but device didn't start working. I guess that's because nstatus keeps dropping low, (device keeps on reseting), so there is no valid program downloaded. 

 So question goes back to why nstatus keeps dropping, even without blaster. That's why I don't think it has any relation with Quartus. (the program we used has been verified well for many times before)  According to handbook, power supply and nconfig could drop down nstatus. I don't know is there any other reason can cause this matter?  thank you!

[Altera_Forum]

I already mentioned the problem of FPGA configuration while AS flash is empty respectively doesn't hold a valid configuration. There may be additional problems in your hardware, but the reported nStatus behaviour is normal operation with an invalid AS configuration, because the FPGA periodically tries a re-configuration.  

 From Quartus Software Hanbook: halt on-chip configuration controller    --- Quote Start ---  Halts the on-chip auto-configuration controller of the FPGA device for AS configuration, or the configuration device for PS or Fast Passive Parallel (FPP) configuration to allow JTAG configuration through a download cable. If you want to configure your FPGA through JTAG while the FPGA MSEL pins are set to AS mode, you should halt the on-chip configuration controller if any of the following circumstances occur: ■ The active serial configuration device connected to your FPGA is blank ■ The active serial configuration device is not present ■ An error occurs during AS configuration prior to JTAG configuration If the MSEL pins are set to PS or FPP mode, halt the configuration controller of the configuration device if an error occurs during PS or FPP configuration prior to JTAG configuration. The FPGA pulls the nSTATUS pin (which is connected to the OE pin of the configuration device) low to disable the configuration device.  --- Quote End ---  

[Altera_Forum]

Hi, FvM, thanks a lot for your patient help. 

 I enlarge the config_done pin's serial resistor, which connect to a NPN with indicating light. The device work well then. I don't know why, but it's OK now.  Thank you very much.