Programmable Devices

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Programmable Devices

Discussions

Configuration Walkthrough

MAX10 User-Specified ADC Logic Simulation Output

Compilation will not complete, possibly due to unconstrained paths

Cyclone 5 custom board PLL issues

Assuming that one wants to use the PCIe capability in the Altera FPGA, what list of t

Beginner in Linux. Need some resource to learn Linux.

Is it OK to use clock in the logic decisions?

Is there any community site or forum for FPGA more popular than Altera Forum?

De0_nano_soc_arduino

emac0 through FPGA

is it a good choice to use max10 in my new project?

5 Gbps USB 3.0 PIPE interface via Cyclone V GT 6 Gbps transceivers?

Cyclone II hex file

Quartus Fitter Crashes (Prime Pro 16.1.0) when compiling for Arria 10 SOC

I can't download Altera Monitor Program on the web

Featured Content

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

EPM3064ATC44-7N and EPM3064ATI44-10N

Deserializers in Agilex 3 series

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage