delay of '< >' and '= !='

[Altera_Forum]

Hi 

Do u know the difference of delay of the comparator? I heard that the '<' or '>'comparator is more delayed than the '='or'!='. Is that true? and why?  Thank U for your attention!

[Altera_Forum]

If you want to understand stuff like this, you need to be able to throw it into a design and analyze it.  

module test ( input [7:0] a_eq, b_eq, a_greater, b_greater, output equal, greater); assign equal = a_eq == b_eq; assign greater = a_greater > b_greater); endmodule  The equality check is nice in that no bit-wise comparison is dependent on any other comparison, i.e. they can all be done independently and then a final check to make sure everyone matches. You basically bit-wise XOR the two values and then OR those values. With 16-inputs in above(8 for each value), if you targeted a Cyclone IV which has a 4 LUT, it would take 4 LUTs for the first stage(each LUT comparing 2 bits) and then a final LUT to make sure they all matched. So 5 LUTs and two levels of logic. A comparison is more complicated since each bit comparison is only dependent on whether the upper bits before it matched. If they did not, then those two bits are a don't care. This makes it more complicated, but synthesis uses the carry chain. It ends up being 8 levels of logic, but with a carry chain can be quite fast and is now independent of place-and-route, since the carry-chain forces the placement. I didn't do timing constraints, but in reality you need to surround the logic with registers, or the timing results will be more dependent on port placement than the actual logic.  I've many times thought about how something would get synthesized, only to find the results very different(and more often than not, better than what I was originally thinking).

[Altera_Forum]

--- Quote Start ---  If you want to understand stuff like this, you need to be able to throw it into a design and analyze it.  module test ( input [7:0] a_eq, b_eq, a_greater, b_greater, output equal, greater); assign equal = a_eq == b_eq; assign greater = a_greater > b_greater); endmodule  The equality check is nice in that no bit-wise comparison is dependent on any other comparison, i.e. they can all be done independently and then a final check to make sure everyone matches. You basically bit-wise XOR the two values and then OR those values. With 16-inputs in above(8 for each value), if you targeted a Cyclone IV which has a 4 LUT, it would take 4 LUTs for the first stage(each LUT comparing 2 bits) and then a final LUT to make sure they all matched. So 5 LUTs and two levels of logic. A comparison is more complicated since each bit comparison is only dependent on whether the upper bits before it matched. If they did not, then those two bits are a don't care. This makes it more complicated, but synthesis uses the carry chain. It ends up being 8 levels of logic, but with a carry chain can be quite fast and is now independent of place-and-route, since the carry-chain forces the placement. I didn't do timing constraints, but in reality you need to surround the logic with registers, or the timing results will be more dependent on port placement than the actual logic.  I've many times thought about how something would get synthesized, only to find the results very different(and more often than not, better than what I was originally thinking).  --- Quote End ---   Thank rysc (http://www.alteraforum.com/forum/member.php?u=100) very much&#65281;Your words help me a lot!! "I've many times thought about how something would get synthesized..." Actually,I thought it at every turn.I guess Altera has its special synthesis algorithm.If only Altera open it!  Best regards!

[Altera_Forum]

Understanding how things get synthesized will make you a better designer(on the flip-side, be careful of getting bogged down in the details). Every tool has their own synthesis algorithms and competes on results, which is one of the reasons its not opened up. You'll also find it very tuned to Altera-only architectures, which with the V series, uses the ALM for logic across the board(Stratix/Arria/Cyclone), which is pretty different than other architectures.

[Altera_Forum]

You better want to do a comparator of value comparing to 2^x, which makes the comparator to check only one bit and leave all LSBs. That's probably the fastest way of comparing.

[Altera_Forum]

yes,a deep understanding of the device architecture actually helps design. 

I'll try to learn more in my work! Thanks !

[Altera_Forum]

I'm afraid not getting your words... 

If I want to compare the 8-bit A and B,the '>' must compare from the [7] to [0]. How "makes the comparator to check only one bit and leave all LSBs"?

[Altera_Forum]

If You need to check all the bits, then this doesn't work.