delayed pulse generator

[Altera_Forum]

hello , i must do a delayed circuit pulse generator.(i can set delay and width of pulse). My code works fine, but quartusII make a warning (complex event). 

can i do this circuit in another mode?  my code:   module GateGENERATORASSER(clk,start,outPulse);  input clk,start; output outPulse; reg started=0; reg outPulse=0;  reg[11:0] Start=0; reg[12:0] Stop=0; reg[11:0] StartREF=10; reg[12:0] StopREF=4700;     always @(negedge start or posedge(Start==StartREF)) //COMPLEX EVENT!! if(Start==StartREF) started<=0; else started<=1;  always @(posedge clk) if(started) Start<=Start+1; else if(Start==StartREF) Start<=0;  always @(posedge clk) if(Start==StartREF) outPulse<=1; else if(Stop==StopREF) begin outPulse<=0; Stop<=0; end else if(outPulse) Stop<=Stop+1;    endmodule

[Altera_Forum]

You can't initialize an input as in: 

reg[11:0] Start=0; reg[12:0] Stop=0; reg[11:0] StartREF=10; reg[12:0] StopREF=4700;  You just need an enabled counter. The counter starts counting the clock cycles when Start goes to '1' when the counter reaches the delay value (depending on the required delay) then outPulse is asserted.  module GateGENERATORASSER(clk,start,outPulse,delay,reset); input reset,clk,start input [7:0] delay; // Maximum 255 clock cycles of delay output outPulse;  reg [7:0] count;   always @(posedge clk) begin if (reset)  count<=8'h00 else   if (start)  count<=count+1;  else  count<=0; end  assign outPulse= (count>delay) ? 1'b1 : 1'b0;  endmodule  This leaves with a precision that is no lower than the clock period. And works if start doesn't do strange things.

[Altera_Forum]

i need a variable delay and a variable width of pulse, but in your code i can set only the delay. 

And the circuit must to be sensitive at negedge of start...   P.S. the initialization of registers works!!  regards

[Altera_Forum]

If you need a variable pulse width then you need another counter  

the starts counting when the first arrives to the delay value.   It's not difficult.   I'm not sure that the initialization of the register works. Even it if does it's surely a bad design procedure.   With reference to the " Complex event" always @(negedge start or posedge(Start==StartREF)) //COMPLEX EVENT!!   if you put two counter in sequence, you don't need anythis like that. Only procedures synchronous with the clock.   Your final assign should look something like: assign outPulse = (cnt1>delay)&&(cont2<pulsewidth) ? 1'b1 : 1b0;

[Altera_Forum]

tnx!! 

but if i want the circuit sensitive at negedge of start? in my case the start signal has a width very short!!

[Altera_Forum]

You need to debounce the start signal. 

PS: I'm assuming your "start" is active low.  This should be a starting point:  reg start_aux = 1'b0; always @ (posedge clk or negedge start)  begin if (!start)   start_aux = 1'b0; else  start_aux = start; end

[Altera_Forum]

tnx rbugalho. 

but i need not use this code: always @ (posedge clk or negedge start)   it create a warning on quartus2.

[Altera_Forum]

Hi,  

that code can be used but it has to follow a specific template.   I don't have Quartus here but, unless I'm seeing something wrong, the piece of code I wrote follows that template.  It should describe a (positive) edge triggered flip-flop with an active low asynchronous reset.