deleting logic increases macrocells?

[Niko3]

Hi,

I have a very curious effect:

The design of my project is a schematic for an EPM3064ATC100. After compilation 51 macrocells from 64 available ones are used. When I remove an AND with 4 inputs and a NAND with 2 inputs 64 macrocells are used - an increase of 13 macrocells!

What happened?

I'd like to know if this is normal?

[Niko3]

Sorry, I changed a little bit more:

I additionally replaced an output by an input.

[ShengN_Intel · Accepted solution]

Hi,

This is possible behavior. The original 51 macrocells likely benefited from logic optimization which AND (4 inputs) and NAND (2 inputs) could have been part of a wider combinational logic structure, allowing the fitter to place more logic in fewer macrocells.

When you removed those gates, the fitter had to restructure the logic, which could have increased the number of macrocells

Thanks,

Regards,

Sheng