dense packing for fourteennm_mlab_cell and not related register

[matota1]

Hi there,

I just wonder if I use asynchronous fourteennm_mlab_cell primitive, will Quartus be able to map independent register to the same mlab cell's ALM/LAB by dense packing feature?

Or using asynchronous MLAB cell causes that registers from the same ALM/LAB are lost forever for mapping purposes?

I found on documentation that:

The LUT, adder, or register output can drive the ALM outputs. Both the LUT or adder and the ALM register can drive out of the ALM simultaneously. Register packing improves device utilization by allowing unrelated register and combinational logic to be packed into a single ALM

does this also apply to stratix 10 MLAB?

I prepared very simple test with asynchronous MLAB with unrelated register which was synthesized to 2xff (one is unrelated, one is hyper-register for datain) and 1x asynchronous mlab:

module top
#(
parameter DATA_WIDTH = 1,
parameter ADDR_SIZE = 4
)
(
input clk,
input we,
input [ADDR_SIZE-1:0] addr,
input [DATA_WIDTH-1:0] di,
output [DATA_WIDTH-1:0] dout,

input r_i,
output reg r_o
);

reg [DATA_WIDTH-1:0] RAM [(2**ADDR_SIZE)-1:0];

always @(posedge clk) begin
if (we) begin
RAM[addr] <= di;
end

end

assign dout = RAM[addr];

always @(posedge clk) begin
r_o <= r_i;
end

endmodule

after implementation in the fit.place.rpt I do not see any dense packing:

; Logic utilization (ALMs needed / total ALMs on device) ; 11 / 933,120 ; < 1 % ;
; ALMs needed [=A-B+C] ; 11 ; ;
; [A] ALMs used in final placement [=a+b+c+d] ; 11 / 933,120 ; < 1 % ;
; [a] ALMs used for LUT logic and register circuitry ; 0 ; ;
; [b] ALMs used for LUT logic ; 0 ; ;
; [c] ALMs used for register circuitry ; 1 ; ;
; [d] ALMs used for memory (up to half of total ALMs) ; 10 ; ;
; [B] Estimate of ALMs recoverable by dense packing ; 0 / 933,120 ; 0 % ;
; Difficulty packing design ; High ; ;

Is this because of MLAB (not combinational logic per se) or the testcase is too small (in terms of resources utilization) for dense packing? Or maybe I need use some implementation options?

Thanks for your help.

Maciej

[RichardTanSY_Intel · Accepted solution]

From the documentation, you can use an MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM. So the tool should be able to get the unrelated register and combinational logic to be packed into a single ALM.

https://www.intel.com/programmable/technical-pdfs/683699.pdf

I think the ALM needed is very low in the design so the tool feel that packing is not necessary.

You may checkout the KDB below for further details on the dense packing.

https://www.intel.com/content/www/us/en/support/programmable/articles/000081441.html

[RichardTanSY_Intel]

Does my latest reply answered your question?

[matota1]

Yes, thank you very much.

[RichardTanSY_Intel]

I’m glad that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.