Hi, Miss/Mr :
i want to get the doc in which there is some description about IO-Column ,Transceivers,PLL distribution , just as tables or diagrams both in logic-organization and physical-planner.
Futher, i am doing job on DDR3 desgining, i am uncertain that muilti-groups( x4 chips exist in each group) can placement in one column ,whithout sharing banks. During the ug-doc<External Memory Handbook Volume Interface1/2/3>, i did not find any assertion about this situation.
That is all, Thanks!
Look forward to help!
Best Wishes to you!
May I know which device you are referring to ? For example, is it Arria 10, Cyclone 10 or etc ?
If you are looking for Arria 10 then you may refer to Chapter 2 of this EMIF Arria 10 user guide which explained about the EMIF architecture and provide descriptions about the I/O column , PLL with the diagrams/layout --> https://www.intel.com/content/www/us/en/programmable/documentation/eqw1503946000045.html#hco14164926...
For the transceiver information , refer to this user guide --> https://www.intel.com/content/www/us/en/programmable/documentation/nik1398707230472.html#nik13987067...
Hope this is helpful.