different width fifo

[Altera_Forum]

So i have a Dual clock FIFO with different input and output width. My input is 32bits and my output is 128. I was wondering what would happen if at some point when there is only 32, 64 or 96 bits of data in the FIFO and I issue a read command what would get out of the 128 port. is it going to be padded with zeros or is it going to repeat the last 32 bits that where entered. or is if going to make the FIFO crash and burn

[Altera_Forum]

Don't wonder, simulate. That is what Modelsim is for :) 

 Cheers, Dave

[Altera_Forum]

I'd say: do not simulate yet. Read the User Manual first. If you still feel like experimenting simulate. It may do what you want it to. But that 'simulated' behaviour is nowhere guaranteed for future releases (this will be unlikely but you never know how clever the synthesiser may get).

[Altera_Forum]

Usually, I would expect the empty flag to remain high until it has an entire output word ready for you. So if you turn the underflow protection on, there wont be a problem, turn it off, and you're gonna get burned.

[Altera_Forum]

thanks guys so i do have underflow protection on. I did some test with singal tap and here is the conclusion i came up with please let me know if it sounds right: 

 - rdempty get asserted when there is not a full word that can be read.  - rdusedw will be at 1 when there is data in the FIFO even tho there is not enough to read a full word  - When i read and the FIFO dose not have 128 bits of data it will pad the rest with the last 32 bits that came in

[Altera_Forum]

I think you have to be careful. Are you using lookahead mode? It shouldnt clear any data from the output if rdempty is asserted. So it probably isnt zero padded, its probably just padded with whatever the old memory contents were, and wont move the memory pointer forward. without the underflow protection, the memory pointer would move. So you havent actually taken a value out of the FIFO.