Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21615 Discussions

facing spi intarface DE2

Altera_Forum
Honored Contributor II
2,112 Views

Hello 

I am very new to Altera and Vhdl pls help 

I want to conenct micro to Dea2 "gpio" pins and implament spi communication and my qauastion is what kind of voltage level my micro should work in order the DE2 will be able to "talk" with it? 

Thx
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
546 Views

Ideally the microcontroller should have 3.3V logic levels. 

 

Probe the signals with an oscilloscope at the DE2 connector and check there is no ringing on the SPI clock signal. If there is, add a series resistor close to the microcontroller board. This will stop the FPGA seeing multiple clock edges. 

 

If you don't have an oscilloscope, then use SignalTap II with a 50MHz clock (whatever the onboard oscillator is) to look at the SPI interface, and zoom into the clock edges to see there is no "glitching". 

 

Cheers, 

Dave
0 Kudos
Altera_Forum
Honored Contributor II
546 Views

Thank you,Do u think maybe it better to use on my micro gpio's insted of spi module and than it will be 3.3 and 0 and on another hand on the DE2 board i also will use the gpio's. 

Thx. 

How hard is to implement and spi master slave on Fpga that will act as an Master that need to mange data transmission from 3 micro's .For example if micro 1 want to talk to micro 2 it sends data to fpga who suppose to monitor it to micro 2. 

Thx.
0 Kudos
Altera_Forum
Honored Contributor II
546 Views

 

--- Quote Start ---  

Thank you,Do u think maybe it better to use on my micro gpio's insted of spi module and than it will be 3.3 and 0 

--- Quote End ---  

 

 

If the micro power supply is 3.3V, then its GPIO and SPI module pins will use 3.3V logic levels. 

 

 

--- Quote Start ---  

 

and on another hand on the DE2 board i also will use the gpio's. 

 

--- Quote End ---  

 

All the DE2 header I/O pins are "GPIO", there's no distinction, eg., an SPI module implemented in the FPGA can use any of the header I/O pins. 

 

 

--- Quote Start ---  

 

How hard is to implement and spi master slave on Fpga that will act as an Master that need to mange data transmission from 3 micro's .For example if micro 1 want to talk to micro 2 it sends data to fpga who suppose to monitor it to micro 2. 

 

--- Quote End ---  

 

It depends on whether you are using the FPGA as a multiplexer to simply connect the SPI signals between micros, or whether you are getting the FPGA to "look" at the SPI data, and then forward that data to the appropriate micro. 

 

In either case, it doesn't sound too difficult. 

 

Cheers, 

Dave
0 Kudos
Reply