differential clock input for EMIF agilex 5

[Dany2]

Hi 

I'm working on the board of the agilex 5 with lpddr4. I want to input a clock from the external clock  generator to the HSIO bank which is connected to the memory chip.

The problem is that I don't understand the definition of the physiscal interface of this input. The IO voltage is 1.1v.

What is the common mode and voltage swing is allowed on this input?

Can I use a signal generator wich is fed from 1.8V and lvds output?

And how to define this pair of pins in Quartus?

Regards

Dany

[sstrell]

The EMIF is usually driven by a PLL clock.  How are you clocking the rest of your design?

[Dany2]

Yes, but I still can use an external clock and connect it to the IP. At least that's what is dome on the evaluation board

[AdzimZM_Intel]

Hi Dany,

I'm not sure if the external clock generator has specific rules but for EMIF IP reference clock, you need to use true differential signaling with differential termination.

As long as the frequency is stable at the desired value, that should be good for EMIF IP.

Agilex 5 device doesn't support single-ended reference clock for EMIF IP.

For external clock generator, it depends on the component requirement. It's not tie to EMIF IP.

For reference, you may check the Agilex 5 Premium Devkit that is using Si5332 for clock generator. https://www.mouser.com/ProductDetail/Skyworks-Solutions-Inc/Si5332E-D-GM1?qs=w%2Fv1CP2dgqoQISLsvW5Sbg%3D%3D

Regards,

Adzim

[FvM]

Hi,
interfacing standard LVDS-output (e.g. 1.8V driver) with HSIO bank requires AC coupling, see GPIO User Guide, paragraph 2.4.2.1f, because LVDS Vocm of 1.2 V exceeds HSIO voltage range.

[Dany2]

Great, thanks