Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

digital clock recovery (synchronization) CDMA

Altera_Forum
Honored Contributor II
1,208 Views

Does anyone have an idea about digital clock recovery (synchronization) in a CDMA wired link?The synchronization uses only the data from the transmitter not its clock...any proposed implementation?

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
518 Views

Clock recovery isn't particularly related to CDMA, but it has to be performed with many serial communication protocols, thus it's a very common problem. 

 

Used techniques are different, depending on the transmission speed, serial protocol and tolerable clock frequency difference. Generally, PLLs are uitilized in most cases, either analog or digital variants. Altera Gigabit transceiver e.g. have dedicated clock recovery hardware.
0 Kudos
Reply