divide by two operation in vhdl

Altera_Forum · ‎02-18-2013

Hai,

I have write vhdl code for divide by two operation. Below is the short code:


SRL16_a:process(CLK)  begin                        --  SRL16
        if CLK'event and CLK='1' then 
            if en='1' and (cycle=0 or cycle=2 or cycle=4 or cycle=6) then     
                sr16<=di & sr16(0 to 14);                  -- shift SRL16          
            end if;
        end if;
    end process;     
    a1<= sr16(ad1);                 -- output from SRL16
SM_B:process(clk,rst)
    begin
        if RST = '1' then      
            di <= (others => '0');          
            bp <= (others => '0');      
            bm <= (others => '0');
        elsif CLK = '1' and CLK'event then      
            if en = '1' then                        
                if     d_signed =0 then
                    di<=unsigned(DATA_IN) - unsigned( a1_2);
                else
                    di<= DATA_IN;
                end if;    
                add_temp<=SXT(di,9)+a1;
                bp<='0'& add_temp(8 downto 1);
                bm<=SXT(di,9)-a1;
                
            end if;
        end if;
    end process;

I try to add to numbers (di & a1), and then divide the sum by 2. When I simulate the testbench code in ModelSim, the values of add_temp and bm is correct. But, the values of bp is wrong (not as manual calculation). I attach the figure. Anyone please help me. Do I make anything wrong?Thank in advance

Altera_Forum · ‎02-18-2013

Hi ,

Your simulation shows that a1 dosent become valid for 08 clock cycles .

If you can send me the complete VHDL files plus test bench i can take out some bugs .

Regards ,

Altera_Forum · ‎02-18-2013

According to my manual calculation, the bp values are as expectable. You are doing a logical shift right, probably you want an arithmetical shift with sign extension?

Altera_Forum · ‎02-18-2013

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Hi , Your simulation shows that a1 dosent become valid for 08 clock cycles . If you can send me the complete VHDL files plus test bench i can take out some bugs . Regards ,

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Hai FPGA_guru011,

I will send to your e-mail. Hope you can helps. Thanks in advance

Altera_Forum · ‎02-18-2013

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According to my manual calculation, the bp values are as expectable. You are doing a logical shift right, probably you want an arithmetical shift with sign extension?

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Hai FvM,

Is it the bp values are exceptable? In my manual calculation (I take one example), add_temp:108+(-25)=83. Then, bp: 83/2=41.5. From the waveform, it seems correct. But, the next values is it should be, add_temp: -25+(-25)=-50. Then, bp: -50/2=-25. And so on. Please correct me. Thank in advance

Altera_Forum · ‎02-18-2013

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Then, bp: -50/2=-25. And so on. Please correct me.

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-25 would be 0x1e7. Due to logic shift right, you get 0x0e7 instead, or 231.

For arithmetic shift, write

bp <= add_temp(8) & add_temp(8 downto 1);

Altera_Forum · ‎02-19-2013

Hai FvM,

Thanks a lot for your explanation. I learn new thing about logic shift and arithmetic shift here. Appreciate your helps. Thank you :)