epcs controller

[Altera_Forum]

I'm trying some informations about EPCS CONTROLLER control word. 

Inside datasheet doesn't speak about meaning of single bit inside EPCS control words.  Somebody knows this bits? I don't understand why altera hide this bits . I have to use it because I have SPI host that must program epcs and I don't use NIOS II inside FPGA but I use just only spi_slave_to_avalon_mm_master_bridge So host microcontroller have to control EPCS controller and I need to know single bit meaning. Somebody can help me? Bye G

[Altera_Forum]

Why don't you use ALTASMI_PARALLEL ? 

It works great.

[Altera_Forum]

even the HAL does not tell everything about the epcs controller, normaly you would think okay that epcs device is an SPI memoy so lets have a look at the possible manufacture datesheets to lern more about it. 

but there is something between this spi functionality and the epcs related pins specially that you cannot add a simple custom spi functionality. it seems to be possible now with cyclone III, but i haven't tryed that

[Altera_Forum]

Hi Amilcar, can You send me an axample with ASMI? 

My problem is: I have to write EPCSand my microcontroller HOST is connecte with FPGA ALTERA with SPI to avalon master bridge. I have to write EPCS. Do You have an example? For MSchmitt: thanks but I haven't to program EPCS directly with SPI HOST. I have HOST connected with FPGA and FPGA have to write EPCS.  Bye G

[Altera_Forum]

Hi Ferraro, 

 EPCS is like a regular SPI flash of STmicro. EPCS controller is a Altera SPI controller and a hidden onchip memory.  So your configuration might look like this,  MPU ->FPGA[ bridge -> avalon MM bus ->Altera SPI master-> ] EPCS  Right?  - Hippo

[Altera_Forum]

Hi Hippo, 

my configuration is different. I have:1 MPU HOST (as SPI master) connected with FPGA (here SPI as slave: spi_slave_to_avalon_mm_master_bridge). FPGA is connected as ACTIVE SERIAL and I have to program EPCS with HOST MPU. This is my problem. Hardware is done and I haven't other possibilities. For this reason I would to know how EPCS CONTROLLER run and control word bit's meaning. In my idea I HAVE TO REALIZE (HOST SOFTWARE): 1. use SOF2FLASH to convert .sof into .flash (S-record) 2. write .flash inside HOST flash (by remote control) 3. software to convert .flash to SPI PHYSICAL LAYER for spi_slave_to_avalon_mm_master_bridge with commands for EPCS CONTROLLER  Can You tell me something about point 3? I have some difficult to find correct use of EPC CONTROLLER. Bye

[Altera_Forum]

Hi Amilcar, 

do You have an example for ALTASMI_PARALLEL? I noted that there isn't ALTASMI_PARALLEL inside SOPC object, so I don't know how can I connect it to my SOPC block. Bye G

[Altera_Forum]

Don't call it epcs. It is just a spi flash, you can find data and app note from stmicro. 

 The method to convert sof to binary data for epcs/spi flash programming is replied in another post from you.  Though your original plan is possible, it is extremely complex and slow. I would suggest another approach, control the spi flash directly. You may instant asmiblock primitive from quartus/libraries/megafunctions, which is just io pins to spi flash.  MPU SPI master -> FPGA[ --> pass through-> asmi ] -> spi flash.   wire MISO,MOSI,SCLK,SS_n;   asmiblock the_tornado_epcs_controller_atom  (  .data0out (MISO),  .dclkin (SCLK),  .oe (1'b0),  .scein (SS_n),  .sdoin (MOSI)  );

[Altera_Forum]

hippo seams to have a nice solution. 

 The one I use assumes that your MPU does not have a SPI port.

[Altera_Forum]

I changed my design . I'm using MPU SPI to connect SPI AVALON MASTER BRIDGE to configure and read/write FPGA adn the same SPI to program EPCS. 

I removed EPCS controller that insime my project is not important.  At hte momento I have this problem: because when HOST MPU is programming EPCS there are a possibility that EPCS should be wrong written, after this operation my board doesn't start more. So I need to implement REMOTE UPDATE : I'm using CYCLONE IV and this is possible. Somebody has some example ? I'm reading altera's datasheet but is not so clear and I would try a simple. Bye G

[Altera_Forum]

Please check an example at 

 http://nioswiki.com/exampledesigns/remote_update/remote_update_for_cyclone_iv_e  The fpga will start with factory configuration, you will need to program remote update core to load user configuration next.  Another suggest, you might add a nios2 core and use spi slave. This will make your fpga a smart peripheral.  MPU SPI Master -> fpga[ spi slave -> nios2 -> onchip mem, rcu, spi flash etc. ]  - Hippo

[Altera_Forum]

Hi Hippo, 

1. I can't implement NIOS II because I havent space inside FPGA 2. When I spoke about REMOTE UPDATE I intended REMOTE UPDATE block inside SOPC. It is an ALTERA BLOCK and I would to use it. Bye G

[Altera_Forum]

The page I mentioned is a remote update core which you can access with spi avalon master bridge. 

 - Hippo

[Altera_Forum]

Yes, it is true but I intended to use REMOTE UPDATE inside SOPC. 

This is Your verilog program but I would to use ALTERA standard block. I read that after CYCLONE III there are possibilities to program multioot system inside EPCS. I read some PDF but at the moment is not so clear for me and I needed some example. Bye G

[Altera_Forum]

The c4up.v is generated using altera megacore wizard. The rcu.v is an implementation similar to the cyc3 of sopc builder because altera didn't release the source. 

 So it is the core for sopc builder. You can look at the driver code of cyc3 and do it in a similar way.  Beside, if there is still a chance touch the hardware, you would be better to use PS mode to configure the fpga (no need the epcs and remote update as AS mode).  - Hippo

[Altera_Forum]

You could also use the ALT_REMOTE megafunction directly. 

The .pdf from it is good, and easy to understand. I used it together with a small (20 lines) state machine, and it gets the job done.