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error loading design in model sim

Altera_Forum
Honored Contributor II
‎08-17-2015 09:31 AM
1,143 Views

hi, 

i am trying to simulate my custom component developed in vhdl language using modelsim. 

i have successfully generated the qsys file and build the NIOS II sbt file. 

but when i tried to simulate by using the option run as NIOS II model sim, its showing the error " error loading design". 

pls help me to resolve this issue.
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Altera_Forum
Honored Contributor II
‎08-18-2015 01:00 AM
406 Views

Probably some screenshots of the errors would be helpful for further understanding.

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