exporting assignment between projects, something wrong ?

[Altera_Forum]

I'm using cyclone III NIOSII embedded evaluation kit with their reference design. 

 I'm starting a new project from the scratch, after finish the SOPC_Builder design I've selected the .vhd file as top of the project.  I've copied all the .tcl files of the previous project to the new project's folder and I've imported the assignments from the original project.  Synthesys is ok but when Quartus is fitting fails for wrong assignments to DDR .  Am I doing Something wrong?

[Altera_Forum]

It's necessary, to check what's wrong in detail, I think. Maybe you changed some design entity name referenced in the tcl files.

[Altera_Forum]

Hi FVM, 

 Then Do I need to remove the references to inexistent entities in .tcl files?  also Do I need to update the new names to the references in .tcl files?

[Altera_Forum]

I don't know in detail. I just imagined that some changes to your design may have invalidated the *.tcl settings, thus something is missing. I expect that the errors report you received gives a hint. Another possible issue is, that you didn't yet connect the DDR instance in your design, so it's removed in compilation.