fir filter for fsk demodulator

[Altera_Forum]

Hi, 

i've realized an i_q demodulator for fsk message. The frequencies for the 0 and for the 1 are spaced 400Hz; the baud rate is up 200baud. The frequencies are in the audio range (for example F0=4050Hz and F1=4450Hz). That kind of demodulator needs two Low Pass filter for the i and q components.  The problem is that in order to obtain an attenuation > 3dB @ 200Hz and >40db @ 400Hz the order of filter implemented is too high (now it is 1000) and the used resources overcome the max allowable by my FPGA (i.e. Memory Bits > 400.000).   Is there any way or another kind of filter that could help me? Any others ideas? Thanks a lot....  My FPGA is cyclone ep4ce6

[Altera_Forum]

--- Quote Start ---  Hi, i've realized an i_q demodulator for fsk message. The frequencies for the 0 and for the 1 are spaced 400Hz; the baud rate is up 200baud. The frequencies are in the audio range (for example F0=4050Hz and F1=4450Hz). That kind of demodulator needs two Low Pass filter for the i and q components.  The problem is that in order to obtain an attenuation > 3dB @ 200Hz and >40db @ 400Hz the order of filter implemented is too high (now it is 1000) and the used resources overcome the max allowable by my FPGA (i.e. Memory Bits > 400.000).   Is there any way or another kind of filter that could help me? Any others ideas? Thanks a lot....    --- Quote End ---    so your high frequency is 4450Hz yet your symbol rate is 200 symbols/sec(baud). I don't get it. what is your sampling rate?

[Altera_Forum]

the sample rate i choose is 200KHz and the highest frequencies for the fsk are around 20KHz... 

What about the solution of CIC? What about the solution of IIR? Let me know...

[Altera_Forum]

--- Quote Start ---  the sample rate i choose is 200KHz and the highest frequencies for the fsk are around 20KHz... What about the solution of CIC? What about the solution of IIR? Let me know...  --- Quote End ---    I am lost with your figures.Let us restart:  adc signal sampling rate = 200KHz f0 = 4.050KHz f1 = 4.450KHz  what is that 20KHz? baud = 200, can't be  IQ demod outputs: IQ demodulator downconverts to what values for f0,f1 you will need to filter the second sideband on each of I and Q after downconversion. So you need to tell us what is f0,f1 after IQ demod and what is sampling rate.

[Altera_Forum]

--- Quote Start ---   what is that 20KHz?  --- Quote End ---   The frequencies for the fsk messagge are in the range 3Khz to 20Khz, so for example a message could be modulated with 4050 for F0 and 4450 for F1 and another message could be modulated with 18000 for F0 and 18400 for F1.    --- Quote Start ---   baud = 200, can't be  --- Quote End ---   the data baud rate is up to 200baud (i.e. from 40Hz to 200Hz)    --- Quote Start ---   IQ demod outputs: IQ demodulator downconverts to what values for f0,f1 you will need to filter the second sideband on each of I and Q after downconversion. So you need to tell us what is f0,f1 after IQ demod and what is sampling rate.  --- Quote End ---   I think i need 2 iq demodulator one for F0 freq and another for f1 signal,is it right? At the moment the sampling rate is 200khz... The last question is not so clear...

[Altera_Forum]

--- Quote Start ---  The frequencies for the fsk messagge are in the range 3Khz to 20Khz, so for example a message could be modulated with 4050 for F0 and 4450 for F1 and another message could be modulated with 18000 for F0 and 18400 for F1.   the data baud rate is up to 200baud (i.e. from 40Hz to 200Hz)   I think i need 2 iq demodulator one for F0 freq and another for f1 signal,is it right? At the moment the sampling rate is 200khz... The last question is not so clear...  --- Quote End ---    ok now it is better (I also correct my questioning of baud as it will be low since each symbol will have many samples).  For the case of f0 at 4050Hz and f1 at 4450 I will use demodulator to downconvert the signal midpoint [(4450+4050)/2 = 4250Hz) to zero frequency i.e. use -4250Hz (or +4250).  I assume your input is real so you have a mirrored copy at +/- 4250 centres.  thus the output of demodulator will consist of two images one copy around zero: 4250 - 4250 = 0 i.e. f0 becomes -200Hz, f1 becomes +200Hz)  and second copy at -4250-(-4250) = -8500Hz centre  You need one IQ demodulator but two filters (I/Q) to remove second copy. now you need to cut somewhere between 200Hz and 8500Hz on your sampling rate of 200Khz. For example cut at 210 and let transition go towards 8300Hz  However this applies to one case of f0/f1. The worst case at 3Khz will move to 6400 so a filter that cuts at 210 and transition band till 6200 will do.  I will see if I can get a sensible filter.

[Altera_Forum]

Your method is very interesting but i have no idea of how to implement it in vhdl (hardware blocks)

[Altera_Forum]

this fir cuts at 200Hz and achieves -40dB at 6300 and should do for worst case 

 h = fir2(100,[0 200/200000 4500/200000 .5]*2,[1 1 0 0]); h = h/sum(h); freqz(h,1,0:.1:6300,200000)

[Altera_Forum]

so the next step is just to implement this kind of filter with altera megafunction (fir compiler) for example or with simulink and test the reponse of iq demod? 

Thanks again

[Altera_Forum]

--- Quote Start ---  so the next step is just to implement this kind of filter with altera megafunction (fir compiler) for example or with simulink and test the reponse of iq demod? Thanks again  --- Quote End ---    yes provided your IQ demod centres signal correctly by multiplying by relevant frequency.  The filter here is meant to remove the second copy(not noise, though it helps noise reduction). once filtered you are left with a signal containing periods of f0/f1 then you can work out a way to convert them to zero and one possibly from gradient of phase.

[Altera_Forum]

additionally you can design your fir as decimator since your 200KHz can be reduced right to 2*20 = 40KHz or so (say 50KHz) then you have decimation factor of 200/50 = 4 

hence your filter mults will go down to 26 per filter

[Altera_Forum]

in this way the parameters to pass to filter after the decimator is: 

Fs=50KHz; Fcut=100Hz Fstop=400Hz  is it right?  Can i use the FIR compiler 2?

[Altera_Forum]

--- Quote Start ---  in this way the parameters to pass to filter after the decimator is: Fs=50KHz; Fcut=100Hz Fstop=400Hz  is it right?  Can i use the FIR compiler 2?  --- Quote End ---    No... Fs is 200KHz Fcutoff ...etc use same filter I gave you (cuts at 200Hz and achieves -40dB at 6300Hz. you can use fir compiler. The output will be decimated to 50Ksps on same system clock of 200Khz (as rate of valid out will indicate)

[Altera_Forum]

i've implemented in this way but it doesn't work 

 https://www.alteraforum.com/forum/attachment.php?attachmentid=9134   i surely don't understand very well...  could you explain me better how set the fir compiler correctly?  I don't see a decimator option....

[Altera_Forum]

In the fir compiler GUI you will see list of single rate, interpolator/decimator. Then you enter the rate as 1 interpolation, 4 decimation. I don't know about your schematic approach. 

 once you run fir compiler it generates hdl file.

[Altera_Forum]

I had a further look at the design. In fact you can decimate much more. 

First your nco should produce the required range and not just for 4050 case. your worst case is 20KHz signal. you will push it to zero so the other sideband goes to 40Khz which is then filtered followed by decimation. Hence you can decimate right to cover the 200Hz signal i.e. 400samples per sec or say 1k i.e. decimation rate of 200K/1 = 200. if you choose this scenario then the filter must cut at 200Hz but sharply at 500Hz instead of 6300 thus it will increase taps but decimation will reduce multipliers by 200 The choice is yours

[Altera_Forum]

i try this solution simulating it in simulink but it doesn't work 

 https://www.alteraforum.com/forum/attachment.php?attachmentid=9140   it works if i put a fir filter after a decimator with FS=50K, Fcut=100 and Fstop=400 but it has 500 taps in order to work correctly...  One last thing that i ommitted: i need to obtain not real demodulation (0 and 1) but also the magnitude of output signal to understand if my input signal is @ full dynamic or not....  Could you check my design and eventually make your corrections? Thanks  i've applied your advise of previous post and it works!!! Great!!!

[Altera_Forum]

--- Quote Start ---  i try this solution simulating it in simulink but it doesn't work  https://www.alteraforum.com/forum/attachment.php?attachmentid=9140   it works if i put a fir filter after a decimator with FS=50K, Fcut=100 and Fstop=400 but it has 500 taps in order to work correctly...  One last thing that i ommitted: i need to obtain not real demodulation (0 and 1) but also the magnitude of output signal to understand if my input signal is @ full dynamic or not....  Could you check my design and eventually make your corrections? Thanks  i've applied your advise of previous post and it works!!! Great!!!  --- Quote End ---    Does it work or not? and what do you mean by work or not work? how do you assess that?  To convert two frequencies to zeros and ones you need to get phase, unwrap it and convert to delay (difference of phase). Each tone will have its unique delay as you can see in the phase response of your filter.  square Magnitude = i^2+Q^2 and I don't think you need to square root it and I don't see why you need it at all.

[Altera_Forum]

it works with this scheme: 

 In_fsk --> sin(f0) cos(f0) mixing --> fir decimation with factor 16 with fs=200k and f(-40db)=6.3K --> fir with fs=200k/16 and f(-40db)=400Hz ---> sqrt(I^2+Q^2)   There is one branch for f0 and onother for f1...  Fir decimatior has about 100 taps and the next one has about 80 taps...the advantage is saving resources    --- Quote Start ---   To convert two frequencies to zeros and ones you need to get phase, unwrap it and convert to delay (difference of phase). Each tone will have its unique delay as you can see in the phase response of your filter.   --- Quote End ---    i don't undestand very well this thing or better i dotn't know how implement it in vhdl... how could i get phase from the fir response? Could you explain me better? Sorry but perhaps since the beginning of this discussion the part that it was less clear is exactly convert two frequencies to zero....(it's my fault) :(  Thanks again

[Altera_Forum]

if you model two frequencies in Matalb, you can see how to convert them to two levels: 

 f1 = exp(j*2*pi*(0:1023)*.1); f2 = exp(j*2*pi*(0:1023)*-.1); f=[f1 f2]; %two symbols plot(diff(unwrap(angle(f))),'.-')  the angle is that of I/Q stream. diff is easy (current sample - next sample). the unwrap and angle are a bit tricky and is usually done in software but you can do it in vhdl by indirect methods. see: http://www.dspguru.com/dsp/tricks/fixed-point-atan2-with-self-normalization    (http://www.dspguru.com/dsp/tricks/fixed-point-atan2-with-self-normalization)