fpga is configured successfully but cannot work

[Altera_Forum]

Hi all 

 My project has two FPGAs and these two FPGAs can be configured separately via their JTAG headers. Besides, the two FPGAs shares an epcs in the multi-device AS configuration mode.  When I download a sof file to one FPGA via the JTAG header. Quartus II programmer shows me "success" but the FPGA doesn't work. The sof file simply turns on/off a led and the pin assignment has been checked. For example:  assign led = 1'b0; // 1'b1  However, after I add a serial flashloader in my top module and download the new design, the FPGA works.   sfl_v sfl_v_inst ( .noe_in(1'b0) );  To my understanding, the serial flashloader is added only when the flash is indirectly configured from JTAG through FPGA. Besides, the configuration file should be jic instead of sof. So what I find in my project is really confused me...  Does anyone have some ideas about my problem? Thanks.

[Altera_Forum]

--- Quote Start ---   My project has two FPGAs and these two FPGAs can be configured separately via their JTAG headers. Besides, the two FPGAs shares an epcs in the multi-device AS configuration mode.   --- Quote End ---    Is "headers" a typo? There should only be one JTAG header. If you have two FPGAs in a chain, and chip-enable-out (nCEO) of the first drives chip-enable-in (nCE) on the second, then regardless of the configuration method, you must configure the first FPGA before configuring the second FPGA.  Is the FPGA you are having a problem with the second FPGA? If so, the fact that the first FPGA is not configured is your problem.  Cheers, Dave

[Altera_Forum]

Having two JTAG headers (one for each FPGA) isn't a problem, just not necessary, and in this case leaves more room for error. Dave is right about the order that the FPGAs need to be configured -- until the nCE of an FPGA is low, the FPGA can't be configured. Also, if the CONF_DONE signals are tied together, neither FPGA will enter "user" mode until both have been configured (if by JTAG, you'd have to load the first, then the second).

[Altera_Forum]

Hi, Dave and fpgajeg 

 Thank you for the help.  After I try to configure the two FPGAs, they both work. (CONF_DONE signal goes high after two FPGAs are configured.)  So now I'm trying to download jic and pof file into the epcs. (jic and pof files are converted from the sof file) For jic file, I connect the usb blaster to the JTAG header. For pof file, I connect the usb blaster to other header for AS mode configuration. Again, the Quartus II programmer shows me "success" but the FPGA doesn't work. CONF_DONE signal is low.

[Altera_Forum]

--- Quote Start ---   After I try to configure the two FPGAs, they both work. (CONF_DONE signal goes high after two FPGAs are configured.)   --- Quote End ---    Ok. Can you confirm that your hardware works, i.e., once both of these FPGAs configured, could you tell that they entered user mode, eg., could you blink an LED on each FPGA, or perhaps access a JTAG component internal to the designs?    --- Quote Start ---   So now I'm trying to download jic and pof file into the epcs. (jic and pof files are converted from the sof file) For jic file, I connect the usb blaster to the JTAG header. For pof file, I connect the usb blaster to other header for AS mode configuration. Again, the Quartus II programmer shows me "success" but the FPGA doesn't work. CONF_DONE signal is low.  --- Quote End ---    This statement is confusing. You stated above that you had two JTAG headers on your board. Are you re-stating now that one is a JTAG header and the other is an Active Serial header? The two headers are identical, but the connections on the PCB are not. Could you post a schematic of the design, or if this is an evaluation board, post a link to its documentation.  Programming an EPCS can be performed using an AS header, or via JTAG using SFL.   Why do you think you need both a .jic file and a .pof file?  Cheers, Dave

[Altera_Forum]

Are you sure you have both FPGA images in your .jic or .pof files (and in the correct order if your FPGAs are different)? If you're using a .jic, you have to be sure the other FPGA is configured (and configured first) because the .jic does two things -- first configures the FPGA (only one) with an image that allows access from the JTAG chain to the EPCS device, then downloads the config file to the EPCS device through the FPGA. If the other FPGA in the chain isn't configured, it's possible that the first step won't complete because the FPGA won't wake up (most likely if CONF_DONE signals are tied together).  

 Assuming there's no problems with the schematic, using AS programming is probably the better method for writing the EPCS device in your case. Make sure both FPGA images are in the .pof file. And make sure you cycle power on the board after programming so the FPGAs load from EPCS.  It sounds like a basic configuration problem.

[Altera_Forum]

Hi, Dave and fpgajeg 

 Sorry for my late reply. I was quite busy for other issues in the past few days.  Let me redescribe my design about the FPGA configuration. 1) My design has two FPGAs. They are both Cyclone IV GX 50. 2) Each FPGA has a JTAG header, so there are two JTAG headers on my pcb. Two FPGAs are not in a JTAG chain. 3) There is another header for AS programming of a serial flash. The serial flash is not EPCS. (In summary, JTAG header 1 is for the first FPGA, JTAG header 2 is for the second FPGA, and the AS header is for the serial flash) 4) The AS configuration circuit is the same as Fig. 8-3 in Cyclone IV configuration handbook. Two FPGAs share a single sof file. (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf) 5) FPGAs can work if FPGAs are configured via the JTAG headers (using sof file). As fpgajeg said, I must configure the first FPGA then the second to make CONF_DONE signal high. 6) FPGAs cannot work no matter jic or pof is used. For jic file, I first configure each FPGA with a design for led blinking. After that, I write jic file to the serial flash via the first JTAG header. For pof file, I write pof file via the AS header.  Hope my statement this time won't be confused anymore. ^^ For now, after I try to configure FPGA from serial flash and repower on the PCB, CONF_DONE is low and nStatus is high for a very short time (approx. 2 us), then goes low for a long time (approx. 110 us), and repeats the same pattern.  (low, low, low, ..., low, high, low, low, low, ..., low, high, ...)  Is this problem related to my adopted serial flash because I'm not using EPCS? Thanks.

[Altera_Forum]

--- Quote Start ---   4) The AS configuration circuit is the same as Fig. 8-3 in Cyclone IV configuration handbook. Two FPGAs share a single sof file. (http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf)   --- Quote End ---    Figure 8-3 shows a configuration scheme where the two FPGAs configure in sequence, i.e., there must be two files in the programming flash. They can be the exact same file, but there needs to be two of them. If you wanted the same file downloaded simultaneously, then you would need to have both chip-enables (nCE) grounded.  If you are loading the serial flash with just a single image, then that is the source of your issue.  Cheers, Dave

[Altera_Forum]

Hi Dave 

 My problem is finally solved. Thanks.

[Altera_Forum]

--- Quote Start ---   My problem is finally solved.   --- Quote End ---   What was the solution?  Cheers, Dave

[Altera_Forum]

Hi Dave 

 I connect both nCE to ground and convert a sof file to pof, as your suggestion.

[Altera_Forum]

--- Quote Start ---   I connect both nCE to ground and convert a sof file to pof, as your suggestion.  --- Quote End ---    Ok. I'm glad to hear you got it working. Thanks for posting your solution - it may be of help to someone else in the future.  Cheers, Dave